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RISC-V: Using fmv.x.w/fmv.w.x rather than fmv.x.s/fmv.s.x

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- fmv.x.s/fmv.s.x renamed to fmv.x.w/fmv.w.x in the latest RISC-V ISA
   manual.

 - Tested rv32gc/rv64gc on bare-metal with qemu.

ChangeLog

gcc/

Kito Cheng  <kito.cheng@sifive.com>

	* config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
	rather than fmv.x.s/fmv.s.x.
This commit is contained in:
Kito Cheng 2020-02-18 13:47:50 +08:00
parent 242b4fb7f4
commit bfe78b0847
2 changed files with 7 additions and 2 deletions
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5
gcc/ChangeLog
View File

@ -1,3 +1,8 @@
2020-01-21 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv.c (riscv_output_move) Using fmv.x.w/fmv.w.x
rather than fmv.x.s/fmv.s.x.
2020-02-18 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd-builtins.def

4
gcc/config/riscv/riscv.c
View File

@ -1917,7 +1917,7 @@ riscv_output_move (rtx dest, rtx src)
if (dest_code == REG && GP_REG_P (REGNO (dest)))
{
if (src_code == REG && FP_REG_P (REGNO (src)))
return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1";
return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1";
if (src_code == MEM)
switch (GET_MODE_SIZE (mode))
@ -1954,7 +1954,7 @@ riscv_output_move (rtx dest, rtx src)
if (FP_REG_P (REGNO (dest)))
{
if (!dbl_p)
return "fmv.s.x\t%0,%z1";
return "fmv.w.x\t%0,%z1";
if (TARGET_64BIT)
return "fmv.d.x\t%0,%z1";
/* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */