reload.c (find_reloads): Don't clear badop if we have a winreg alternative...
* reload.c (find_reloads): Don't clear badop if we have a winreg alternative, but not win, and the class only has fixed regs. * hard-reg-set.h (class_only_fixed_regs): Declare. * reginfo.c (class_only_fixed_regs): New array. (init_reg_sets_1): Initialize it. * config/arm/arm.md (arm_addsi3, thumb1_addsi3, arm_subsi3_insn): Don't discourage alternatives using the stack pointer. testsuite/ * gcc.dg/pr32370.c: Allow another kind of error message. From-SVN: r162019
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@ -1,3 +1,14 @@
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2010-07-09 Bernd Schmidt <bernds@codesourcery.com>
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* reload.c (find_reloads): Don't clear badop if we have a
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winreg alternative, but not win, and the class only has fixed
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regs.
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* hard-reg-set.h (class_only_fixed_regs): Declare.
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* reginfo.c (class_only_fixed_regs): New array.
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(init_reg_sets_1): Initialize it.
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* config/arm/arm.md (arm_addsi3, thumb1_addsi3, arm_subsi3_insn): Don't
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discourage alternatives using the stack pointer.
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2010-07-09 Richard Guenther <rguenther@suse.de>
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* gimple.c (struct type_fixup_s): New struct and VEC type.
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@ -610,9 +610,9 @@
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;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will
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;; put the duplicated register first, and not try the commutative version.
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(define_insn_and_split "*arm_addsi3"
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[(set (match_operand:SI 0 "s_register_operand" "=r, !k, r,r, !k,r")
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(plus:SI (match_operand:SI 1 "s_register_operand" "%rk,!k, r,rk,!k,rk")
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(match_operand:SI 2 "reg_or_int_operand" "rI, rI,!k,L, L,?n")))]
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[(set (match_operand:SI 0 "s_register_operand" "=r, k,r,r, k,r")
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(plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k,rk")
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(match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,L, L,?n")))]
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"TARGET_32BIT"
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"@
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add%?\\t%0, %1, %2
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@ -637,14 +637,10 @@
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(set_attr "predicable" "yes")]
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)
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;; Register group 'k' is a single register group containing only the stack
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;; register. Trying to reload it will always fail catastrophically,
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;; so never allow those alternatives to match if reloading is needed.
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(define_insn_and_split "*thumb1_addsi3"
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[(set (match_operand:SI 0 "register_operand" "=l,l,l,*rk,*hk,l,!k,l,l")
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(plus:SI (match_operand:SI 1 "register_operand" "%0,0,l,*0,*0,!k,!k,0,l")
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(match_operand:SI 2 "nonmemory_operand" "I,J,lL,*hk,*rk,!M,!O,Pa,Pb")))]
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[(set (match_operand:SI 0 "register_operand" "=l,l,l,*rk,*hk,l,k,l,l")
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(plus:SI (match_operand:SI 1 "register_operand" "%0,0,l,*0,*0,k,k,0,l")
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(match_operand:SI 2 "nonmemory_operand" "I,J,lL,*hk,*rk,M,O,Pa,Pb")))]
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"TARGET_THUMB1"
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"*
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static const char * const asms[] =
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@ -1089,8 +1085,8 @@
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; ??? Check Thumb-2 split length
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(define_insn_and_split "*arm_subsi3_insn"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r,rk,r,r")
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(minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,!k,?n,r")
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(match_operand:SI 2 "reg_or_int_operand" "r,rI, r, r,?n")))]
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(minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,k,?n,r")
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(match_operand:SI 2 "reg_or_int_operand" "r,rI,r, r,?n")))]
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"TARGET_32BIT"
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"@
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rsb%?\\t%0, %2, %1
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@ -643,6 +643,10 @@ extern int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
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extern HARD_REG_SET reg_class_contents[N_REG_CLASSES];
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/* For each reg class, a boolean saying whether the class contains only
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fixed registers. */
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extern bool class_only_fixed_regs[N_REG_CLASSES];
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/* For each reg class, number of regs it contains. */
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extern unsigned int reg_class_size[N_REG_CLASSES];
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@ -141,6 +141,10 @@ int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
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/* For each reg class, a HARD_REG_SET saying which registers are in it. */
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HARD_REG_SET reg_class_contents[N_REG_CLASSES];
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/* For each reg class, a boolean saying whether the class contains only
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fixed registers. */
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bool class_only_fixed_regs[N_REG_CLASSES];
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/* The same information, but as an array of unsigned ints. We copy from
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these unsigned ints to the table above. We do this so the tm.h files
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do not have to be aware of the wordsize for machines with <= 64 regs.
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memset (reg_class_size, 0, sizeof reg_class_size);
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for (i = 0; i < N_REG_CLASSES; i++)
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for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
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if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
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reg_class_size[i]++;
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{
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bool any_nonfixed = false;
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for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
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if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
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{
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reg_class_size[i]++;
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if (!fixed_regs[j])
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any_nonfixed = true;
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}
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class_only_fixed_regs[i] = !any_nonfixed;
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}
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/* Initialize the table of subunions.
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reg_class_subunion[I][J] gets the largest-numbered reg-class
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@ -3470,7 +3470,8 @@ find_reloads (rtx insn, int replace, int ind_levels, int live_known,
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/* If this operand could be handled with a reg,
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and some reg is allowed, then this operand can be handled. */
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if (winreg && this_alternative[i] != NO_REGS)
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if (winreg && this_alternative[i] != NO_REGS
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&& (win || !class_only_fixed_regs[this_alternative[i]]))
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badop = 0;
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/* Record which operands fit this alternative. */
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@ -1,3 +1,7 @@
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2010-07-09 Bernd Schmidt <bernds@codesourcery.com>
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* gcc.dg/pr32370.c: Allow another kind of error message.
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2010-07-09 Eric Botcazou <ebotcazou@adacore.com>
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* gnat.dg/atomic3.adb: New test.
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@ -19,7 +19,7 @@ unsigned int
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foo (TYPE port)
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{
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unsigned int v;
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__asm__ __volatile__ ("" : C (v) : "Nd" (port)); /* { dg-error "while reloading\|has impossible" } */
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__asm__ __volatile__ ("" : C (v) : "Nd" (port)); /* { dg-error "while reloading\|has impossible\|inconsistent operand constraints" } */
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return v;
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}
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