rs6000.c (rs6000_hard_regno_mode_ok): Force TDmode regnos into even/odd register pairs.
* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Force TDmode regnos into even/odd register pairs. * config/rs6000/rs6000.h [SLOW_UNALIGNED_ACCESS]: Treat DDmode and TDmode similar to the other floating point modes. [SECONDARY_MEMORY_NEEDED]: Treat DDmode similar to DFmode. * config/rs6000/dfp.md (negdd2, absdd2, negtd2, abstd2): New define_expand's. (negdd2_fpr, absdd2_fpr, nabsdd2_fpr, negtd2_fpr, abstd2_fpr, nabstd2_fpr, movdd_hardfloat64_mfpgpr): New define_insn's. (movdd_hardfloat64): Use TARGET_MFPGPR. From-SVN: r123916
This commit is contained in:
parent
ea30850a82
commit
c092b0457f
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@ -1,3 +1,16 @@
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2007-04-17 Peter Bergner <bergner@vnet.ibm.com>
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* config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok): Force TDmode
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regnos into even/odd register pairs.
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* config/rs6000/rs6000.h [SLOW_UNALIGNED_ACCESS]: Treat DDmode and
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TDmode similar to the other floating point modes.
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[SECONDARY_MEMORY_NEEDED]: Treat DDmode similar to DFmode.
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* config/rs6000/dfp.md (negdd2, absdd2, negtd2, abstd2): New
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define_expand's.
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(negdd2_fpr, absdd2_fpr, nabsdd2_fpr, negtd2_fpr, abstd2_fpr,
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nabstd2_fpr, movdd_hardfloat64_mfpgpr): New define_insn's.
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(movdd_hardfloat64): Use TARGET_MFPGPR.
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2007-04-17 Bernd Schmidt <bernd.schmidt@analog.com>
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* reload1.c (delete_output_reload): Don't count output in n_inherited.
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@ -21,6 +21,39 @@
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;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
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;; MA 02110-1301, USA.
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(define_expand "negdd2"
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[(set (match_operand:DD 0 "gpc_reg_operand" "")
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(neg:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
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"")
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(define_insn "*negdd2_fpr"
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[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
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(neg:DD (match_operand:DD 1 "gpc_reg_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"fneg %0,%1"
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[(set_attr "type" "fp")])
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(define_expand "absdd2"
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[(set (match_operand:DD 0 "gpc_reg_operand" "")
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(abs:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
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"")
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(define_insn "*absdd2_fpr"
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[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
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(abs:DD (match_operand:DD 1 "gpc_reg_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"fabs %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "*nabsdd2_fpr"
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[(set (match_operand:DD 0 "gpc_reg_operand" "=f")
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(neg:DD (abs:DD (match_operand:DF 1 "gpc_reg_operand" "f"))))]
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"fnabs %0,%1"
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[(set_attr "type" "fp")])
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(define_expand "movdd"
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[(set (match_operand:DD 0 "nonimmediate_operand" "")
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(match_operand:DD 1 "any_operand" ""))]
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@ -252,10 +285,36 @@
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; ld/std require word-aligned displacements -> 'Y' constraint.
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; List Y->r and r->Y before r->r for reload.
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(define_insn "*movdd_hardfloat64_mfpgpr"
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[(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
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(match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
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"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
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&& (gpc_reg_operand (operands[0], DDmode)
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|| gpc_reg_operand (operands[1], DDmode))"
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"@
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std%U0%X0 %1,%0
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ld%U1%X1 %0,%1
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mr %0,%1
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fmr %0,%1
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lfd%U1%X1 %0,%1
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stfd%U0%X0 %1,%0
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mt%0 %1
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mf%1 %0
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{cror 0,0,0|nop}
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#
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#
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#
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mftgpr %0,%1
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mffgpr %0,%1"
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[(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
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(set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
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; ld/std require word-aligned displacements -> 'Y' constraint.
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; List Y->r and r->Y before r->r for reload.(define_insn "*movdd_hardfloat64"
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(define_insn "*movdd_hardfloat64"
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[(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
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(match_operand:DD 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
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"TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
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&& (gpc_reg_operand (operands[0], DDmode)
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|| gpc_reg_operand (operands[1], DDmode))"
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"@
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@ -293,6 +352,39 @@
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[(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
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(set_attr "length" "4,4,4,4,4,8,12,16,4")])
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(define_expand "negtd2"
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[(set (match_operand:TD 0 "gpc_reg_operand" "")
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(neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
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"")
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(define_insn "*negtd2_fpr"
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[(set (match_operand:TD 0 "gpc_reg_operand" "=f")
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(neg:TD (match_operand:TD 1 "gpc_reg_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"fneg %0,%1"
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[(set_attr "type" "fp")])
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(define_expand "abstd2"
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[(set (match_operand:TD 0 "gpc_reg_operand" "")
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(abs:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
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"")
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(define_insn "*abstd2_fpr"
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[(set (match_operand:TD 0 "gpc_reg_operand" "=f")
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(abs:TD (match_operand:TD 1 "gpc_reg_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"fabs %0,%1"
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[(set_attr "type" "fp")])
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(define_insn "*nabstd2_fpr"
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[(set (match_operand:TD 0 "gpc_reg_operand" "=f")
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(neg:TD (abs:TD (match_operand:DF 1 "gpc_reg_operand" "f"))))]
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"fnabs %0,%1"
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[(set_attr "type" "fp")])
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(define_expand "movtd"
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[(set (match_operand:TD 0 "general_operand" "")
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(match_operand:TD 1 "any_operand" ""))]
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@ -1134,6 +1134,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
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if (FP_REGNO_P (regno))
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return
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(SCALAR_FLOAT_MODE_P (mode)
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&& (mode != TDmode || (regno % 2) == 0)
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&& mode != SDmode
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&& FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
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|| (GET_MODE_CLASS (mode) == MODE_INT
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@ -590,6 +590,7 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
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#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
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(STRICT_ALIGNMENT \
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|| (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
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|| (MODE) == DDmode || (MODE) == TDmode \
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|| (MODE) == DImode) \
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&& (ALIGN) < 32))
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#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
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((CLASS1) != (CLASS2) && (((CLASS1) == FLOAT_REGS \
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&& (!TARGET_MFPGPR || !TARGET_POWERPC64 \
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|| ((MODE != DFmode) && (MODE != DImode)))) \
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|| ((MODE != DFmode) \
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&& (MODE != DDmode) \
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&& (MODE != DImode)))) \
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|| ((CLASS2) == FLOAT_REGS \
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&& (!TARGET_MFPGPR || !TARGET_POWERPC64 \
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|| ((MODE != DFmode) && (MODE != DImode)))) \
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|| ((MODE != DFmode) \
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&& (MODE != DDmode) \
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&& (MODE != DImode)))) \
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|| (CLASS1) == ALTIVEC_REGS \
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|| (CLASS2) == ALTIVEC_REGS))
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