x86: fix CVT{,T}PD2PI insns
With just an "m" constraint misaligned memory operands won't be forced into a register, and hence cause #GP. So far this was guaranteed only in the case that CVT{,T}PD2DQ were chosen (which looks to be the case on x86-64 only). Switch the second alternative to Bm and also replace nonimmediate_operand by vector_operand. From-SVN: r272780
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2019-06-28 Jan Beulich <jbeulich@suse.com>
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* config/i386/sse.md (sse2_cvtpd2pi, sse2_cvttpd2pi): Use
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vector_operand plus, on both alternatives, "Bm" constraint.
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2019-06-28 Dennis Zhang <dennis.zhang@arm.com>
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* config/arm/arm.md: Remove redundant constraints from
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@ -5505,7 +5505,7 @@
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(define_insn "sse2_cvtpd2pi"
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[(set (match_operand:V2SI 0 "register_operand" "=v,?!y")
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(unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "vBm,xm")]
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(unspec:V2SI [(match_operand:V2DF 1 "vector_operand" "vBm,xBm")]
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UNSPEC_FIX_NOTRUNC))]
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"TARGET_SSE2"
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"@
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(define_insn "sse2_cvttpd2pi"
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[(set (match_operand:V2SI 0 "register_operand" "=v,?!y")
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(fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "vBm,xm")))]
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(fix:V2SI (match_operand:V2DF 1 "vector_operand" "vBm,xBm")))]
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"TARGET_SSE2"
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"@
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* return TARGET_AVX ? \"vcvttpd2dq{x}\t{%1, %0|%0, %1}\" : \"cvttpd2dq\t{%1, %0|%0, %1}\";
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2019-06-28 Jan Beulich <jbeulich@suse.com>
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* gcc.target/i386/cvtpd2pi: New.
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2019-06-27 Jakub Jelinek <jakub@redhat.com>
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PR c++/91024
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