Do better scheduling of floating point instructions
From-SVN: r12083
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b0b61fc464
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c1aef54de3
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@ -91,9 +91,11 @@
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;; rte return from exception
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;; sfunc special function call with known used registers
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;; call function call
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;; fp floating point
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;; fdiv floating point divide (or square root)
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(define_attr "type"
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"cbranch,jump,arith,other,load,store,move,smpy,dmpy,return,pload,pstore,pcload,rte,sfunc,call"
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"cbranch,jump,arith,other,load,store,move,smpy,dmpy,return,pload,pstore,pcload,rte,sfunc,call,fp,fdiv"
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(const_string "other"))
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; If a conditional branch destination is within -252..258 bytes away
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@ -137,12 +139,20 @@
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;; (define_function_unit {name} {num-units} {n-users} {test}
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;; {ready-delay} {issue-delay} [{conflict-list}])
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;; ??? These are probably not correct.
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(define_function_unit "memory" 1 0 (eq_attr "type" "load,pcload,pload") 2 2)
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;; Load and store instructions save a cycle if they are aligned on a
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;; four byte boundary. Using a function unit for stores encourages
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;; gcc to separate load and store instructions by one instruction,
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;; which makes it more likely that the linker will be able to word
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;; align them when relaxing.
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(define_function_unit "memory" 1 0
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(eq_attr "type" "load,pcload,pload,store,pstore") 2 2)
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;; ??? These are approximations.
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(define_function_unit "mpy" 1 0 (eq_attr "type" "smpy") 2 2)
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(define_function_unit "mpy" 1 0 (eq_attr "type" "dmpy") 3 3)
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;; ??? Must define SH3E function units.
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(define_function_unit "fp" 1 0 (eq_attr "type" "fp") 2 1)
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(define_function_unit "fp" 1 0 (eq_attr "type" "fdiv") 13 12)
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; Definitions for filling branch delay slots.
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@ -1460,7 +1470,7 @@
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mov.l %1,%0
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flds %1,fpul\;sts fpul,%0
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lds %1,fpul\;fsts fpul,%0"
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[(set_attr "type" "move,move,move,move,load,store,load,store,move,move")
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[(set_attr "type" "move,move,fp,fp,load,store,load,store,move,fp")
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(set_attr "length" "*,*,*,*,*,*,*,*,4,4")])
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(define_expand "movsf"
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@ -2042,21 +2052,24 @@
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(plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
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(match_operand:SF 2 "arith_reg_operand" "f")))]
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"TARGET_SH3E"
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"fadd %2,%0")
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"fadd %2,%0"
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[(set_attr "type" "fp")])
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(define_insn "subsf3"
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[(set (match_operand:SF 0 "arith_reg_operand" "=f")
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(minus:SF (match_operand:SF 1 "arith_reg_operand" "0")
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(match_operand:SF 2 "arith_reg_operand" "f")))]
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"TARGET_SH3E"
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"fsub %2,%0")
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"fsub %2,%0"
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[(set_attr "type" "fp")])
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(define_insn "mulsf3"
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[(set (match_operand:SF 0 "arith_reg_operand" "=f")
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(mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
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(match_operand:SF 2 "arith_reg_operand" "f")))]
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"TARGET_SH3E"
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"fmul %2,%0")
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"fmul %2,%0"
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[(set_attr "type" "fp")])
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(define_insn "*macsf3"
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[(set (match_operand:SF 0 "arith_reg_operand" "=f")
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@ -2064,14 +2077,16 @@
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(match_operand:SF 2 "arith_reg_operand" "f"))
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(match_operand:SF 3 "arith_reg_operand" "0")))]
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"TARGET_SH3E"
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"fmac fr0,%2,%0")
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"fmac fr0,%2,%0"
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[(set_attr "type" "fp")])
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(define_insn "divsf3"
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[(set (match_operand:SF 0 "arith_reg_operand" "=f")
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(div:SF (match_operand:SF 1 "arith_reg_operand" "0")
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(match_operand:SF 2 "arith_reg_operand" "f")))]
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"TARGET_SH3E"
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"fdiv %2,%0")
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"fdiv %2,%0"
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[(set_attr "type" "fdiv")])
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;; ??? This is the right solution, but it fails because the movs[if] patterns
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;; silently clobber FPUL (r22) for int<->fp moves. Thus we can not explicitly
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@ -2096,7 +2111,8 @@
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(float:SF (match_operand:SI 1 "arith_reg_operand" "r")))]
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"TARGET_SH3E"
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"lds %1,fpul\;float fpul,%0"
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[(set_attr "length" "4")])
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[(set_attr "length" "4")
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(set_attr "type" "fp")])
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;; ??? This is the right solution, but it fails because the movs[if] patterns
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;; silently clobber FPUL (r22) for int<->fp moves. Thus we can not explicitly
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@ -2121,7 +2137,8 @@
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(fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))]
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"TARGET_SH3E"
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"ftrc %1,fpul\;sts fpul,%0"
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[(set_attr "length" "4")])
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[(set_attr "length" "4")
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(set_attr "type" "move")])
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;; ??? This should be SFmode not SImode in the compare, but that would
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;; require fixing the branch patterns too.
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@ -2129,7 +2146,8 @@
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[(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
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(match_operand:SF 1 "arith_reg_operand" "f")))]
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"TARGET_SH3E"
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"fcmp/gt %1,%0")
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"fcmp/gt %1,%0"
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[(set_attr "type" "fp")])
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;; ??? This should be SFmode not SImode in the compare, but that would
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;; require fixing the branch patterns too.
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@ -2137,7 +2155,8 @@
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[(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
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(match_operand:SF 1 "arith_reg_operand" "f")))]
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"TARGET_SH3E"
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"fcmp/eq %1,%0")
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"fcmp/eq %1,%0"
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[(set_attr "type" "fp")])
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(define_expand "cmpsf"
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[(set (reg:SI 18) (compare (match_operand:SF 0 "arith_operand" "")
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@ -2154,19 +2173,22 @@
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[(set (match_operand:SF 0 "arith_reg_operand" "=f")
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(neg:SF (match_operand:SF 1 "arith_reg_operand" "0")))]
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"TARGET_SH3E"
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"fneg %0")
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"fneg %0"
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[(set_attr "type" "fp")])
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(define_insn "sqrtsf2"
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[(set (match_operand:SF 0 "arith_reg_operand" "=f")
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(sqrt:DF (match_operand:SF 1 "arith_reg_operand" "0")))]
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"TARGET_SH3E"
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"fsqrt %0")
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"fsqrt %0"
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[(set_attr "type" "fdiv")])
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(define_insn "abssf2"
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[(set (match_operand:SF 0 "arith_reg_operand" "=f")
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(abs:SF (match_operand:SF 1 "arith_reg_operand" "0")))]
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"TARGET_SH3E"
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"fabs %0")
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"fabs %0"
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[(set_attr "type" "fp")])
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;; -------------------------------------------------------------------------
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;; Peepholes
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