(reload_outhi): New pattern.
(movhi): Handle reloads better. (restorehi): Delete. Also tidy up commented out code. (call): Make this a define_expand. (matcher for above): only accept MEM(reg) (call_value): Handle as for (call). From-SVN: r5810
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@ -2410,52 +2410,6 @@
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"
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[(set_attr "conds" "set")])
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;; XXX The movhi stuff isn't as correct or as nice as it could be...
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;; Subroutine to load a half word into a register from memory.
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;; Operand 0 is the destination register (HImode).
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;; Operand 1 is the source address (SImode).
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;; Operand 2 is a temporary (SImode).
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;;(define_expand "loadhi"
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;; [;; load the whole word (ARM realigns it if not on word boundary)
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;; (set (match_operand:SI 2 "s_register_operand" "")
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;; (mem:SI (match_operand:SI 1 "address_operand" "")))
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;; ;; quietly forget the upper 16 bits
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;; (set (match_operand:HI 0 "s_register_operand" "")
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;; (subreg:HI (match_dup 2) 0))]
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;; ""
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;; ""
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;;)
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;; Load op0 from mem:op1. Subroutine in case we're reloading and the normal
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;; loadhi is not allowed.
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;;(define_expand "reloadhi"
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;; [(set (reg:SI 10)
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;; (mem:SI (match_operand:SI 1 "address_operand" "")))
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;; (set (match_operand:HI 0 "s_register_operand" "")
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;; (subreg:HI (reg:SI 10) 0))]
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;; "" "")
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;; Store op0 into mem:op1. Subroutine in case we're reloading and the normal
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;; storehi is not allowed.
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(define_expand "restorehi"
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[(set (mem:QI (match_operand:SI 1 "" ""))
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(match_dup 2))
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(set (reg:SI 10)
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(ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
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(set (mem:QI (match_dup 3))
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(reg:QI 10))]
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""
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"
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{
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operands[2] = gen_lowpart (QImode, operands[0]);
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operands[0] = gen_lowpart (SImode, operands[0]);
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operands[3] = plus_constant (operands[1], 1);
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}")
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;; Subroutine to store a half word from a register into memory.
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;; Operand 0 is the source register (HImode)
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;; Operand 1 is the destination address in a register (SImode)
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@ -2525,12 +2479,7 @@
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rtx insn;
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if (reload_in_progress || reload_completed)
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{
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if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == REG)
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insn = gen_restorehi (operands[1], XEXP (operands[0], 0));
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else
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insn = gen_rtx (SET, VOIDmode, operands[0], operands[1]);
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}
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insn = gen_rtx (SET, VOIDmode, operands[0], operands[1]);
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else
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{
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if (GET_CODE (operands[0]) == MEM)
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@ -2611,6 +2560,16 @@
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"
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[(set_attr "type" "*,*,load,store1")])
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(define_expand "reload_outhi"
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[(parallel [(match_operand:HI 0 "reload_memory_operand" "=o")
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(match_operand:HI 1 "s_register_operand" "r")
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(match_operand:SI 2 "s_register_operand" "=&r")])]
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""
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"
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arm_reload_out_hi (operands);
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DONE;
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")
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(define_expand "movqi"
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[(set (match_operand:QI 0 "general_operand" "")
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(match_operand:QI 1 "general_operand" ""))]
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@ -3724,9 +3683,16 @@
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return (arm_output_asm_insn (\"b\\t%l0\", operands));
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}")
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(define_insn "call"
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[(call (match_operand 0 "memory_operand" "m")
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(match_operand 1 "general_operand" "g"))
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(define_expand "call"
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[(parallel [(call (match_operand 0 "memory_operand" "")
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(match_operand 1 "general_operand" ""))
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(clobber (reg:SI 14))])]
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""
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"")
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(define_insn ""
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[(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
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(match_operand 1 "" "g"))
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(clobber (reg:SI 14))]
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""
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"*
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@ -3755,10 +3721,18 @@
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(set_attr "length" "3")
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(set_attr "type" "call")])
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(define_insn "call_value"
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(define_expand "call_value"
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[(parallel [(set (match_operand 0 "" "=rf")
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(call (match_operand 1 "memory_operand" "m")
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(match_operand 2 "general_operand" "g")))
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(clobber (reg:SI 14))])]
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""
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"")
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(define_insn ""
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[(set (match_operand 0 "" "=rf")
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(call (match_operand 1 "memory_operand" "m")
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(match_operand 2 "general_operand" "g")))
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(call (mem:SI (match_operand:SI 1 "s_register_operand" "r"))
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(match_operand 2 "general_operand" "g")))
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(clobber (reg:SI 14))]
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""
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"*
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