i386.c (processor_target_table): Add skylake_cost for skylake-avx512.
* config/i386/i386.c (processor_target_table): Add skylake_cost for skylake-avx512. * config/i386/x86-tune-costs.h (skylake_memcpy, skylake_memset, skylake_cost): New. * config/i386/driver-i386.c (host_detect_local_cpu): Detect skylake-avx512. * config.gcc: Add -march=cannonlake. * config/i386/driver-i386.c (host_detect_local_cpu): Detect cannonlake. * config/i386/i386-c.c (ix86_target_macros_internal): Handle cannonlake. * config/i386/i386.c (processor_costs): Add m_CANNONLAKE. (PTA_CANNONLAKE): New. (processor_target_table): Add cannonlake. (ix86_option_override_internal): Ditto. (fold_builtin_cpu): Ditto. (get_builtin_code_for_version): Handle cannonlake. (M_INTEL_COREI7_CANNONLAKE): New. * config/i386/i386.h (TARGET_CANNONLAKE, PROCESSOR_CANNONLAKE): New. * doc/invoke.texi: Add -march=cannonlake. gcc/testsuite/ * gcc.target/i386/funcspec-56.inc: Handle new march. * g++.dg/ext/mv16.C: Ditto. libgcc/ * config/i386/cpuinfo.c (get_intel_cpu): Handle cannonlake. * config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_CANNONLAKE. From-SVN: r255155
This commit is contained in:
Uros Bizjak
parent
8c7dbea9f1
commit
c234d8319b
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@ -1,4 +1,31 @@
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2017-11-14 Boris Kolpackov <boris@codesynthesis.com>
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2017-11-26 Julia Koval <julia.koval@intel.com>
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* config/i386/i386.c (processor_target_table): Add skylake_cost for
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skylake-avx512.
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* config/i386/x86-tune-costs.h (skylake_memcpy, skylake_memset,
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skylake_cost): New.
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2017-11-26 Julia Koval <julia.koval@intel.com>
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* config/i386/driver-i386.c (host_detect_local_cpu):
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Detect skylake-avx512.
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2017-11-26 Julia Koval <julia.koval@intel.com>
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* config.gcc: Add -march=cannonlake.
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* config/i386/driver-i386.c (host_detect_local_cpu): Detect cannonlake.
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* config/i386/i386-c.c (ix86_target_macros_internal): Handle cannonlake.
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* config/i386/i386.c (processor_costs): Add m_CANNONLAKE.
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(PTA_CANNONLAKE): New.
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(processor_target_table): Add cannonlake.
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(ix86_option_override_internal): Ditto.
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(fold_builtin_cpu): Ditto.
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(get_builtin_code_for_version): Handle cannonlake.
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(M_INTEL_COREI7_CANNONLAKE): New.
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* config/i386/i386.h (TARGET_CANNONLAKE, PROCESSOR_CANNONLAKE): New.
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* doc/invoke.texi: Add -march=cannonlake.
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2017-11-14 Boris Kolpackov <boris@codesynthesis.com>
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* plugin.c (add_new_plugin): Use platform-specific library extensions.
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(try_init_one_plugin): Alternative implementation for MinGW.
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@ -69,12 +96,12 @@
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2017-11-23 Julia Koval <julia.koval@intel.com>
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config/i386/avx512vbmi2intrin.h (_mm512_mask_expand_epi8,
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* config/i386/avx512vbmi2intrin.h (_mm512_mask_expand_epi8,
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_mm512_maskz_expand_epi8, _mm512_mask_expandloadu_epi8,
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_mm512_maskz_expandloadu_epi8, _mm512_mask_expand_epi16,
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_mm512_maskz_expand_epi16, _mm512_mask_expandloadu_epi16,
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_mm512_maskz_expandloadu_epi16): New intrinsics.
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config/i386/avx512vbmi2vlintrin.h (_mm_mask_expand_epi8,
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* config/i386/avx512vbmi2vlintrin.h (_mm_mask_expand_epi8,
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_mm_maskz_expand_epi8, _mm_mask_expandloadu_epi8,
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_mm_maskz_expandloadu_epi8, _mm_mask_expand_epi16,
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_mm_maskz_expand_epi16, _mm_mask_expandloadu_epi16,
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@ -83,33 +110,33 @@
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_mm256_maskz_expandloadu_epi16, _mm256_mask_expand_epi8,
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_mm256_maskz_expand_epi8, _mm256_mask_expandloadu_epi8,
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_mm256_maskz_expandloadu_epi8): New intrinsics.
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config/i386/i386-builtin-types.def (V64QI_FTYPE_PCV64QI_V64QI_UDI,
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* config/i386/i386-builtin-types.def (V64QI_FTYPE_PCV64QI_V64QI_UDI,
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V32HI_FTYPE_PCV32HI_V32HI_USI, V32QI_FTYPE_PCV32QI_V32QI_USI,
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V16HI_FTYPE_PCV16HI_V16HI_UHI, V16QI_FTYPE_PCV16QI_V16QI_UHI,
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V8HI_FTYPE_PCV8HI_V8HI_UQI): New types.
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config/i386/i386.c (ix86_expand_special_args_builtin): Use new types.
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config/i386/sse.md (VI248_VLBW): New iterator.
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* config/i386/i386.c (ix86_expand_special_args_builtin): Use new types.
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* config/i386/sse.md (VI248_VLBW): New iterator.
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(expand<mode>_mask, expand<mode>_maskz): New patterns.
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2017-11-23 Julia Koval <julia.koval@intel.com>
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config.gcc (avx512vbmi2intrin.h, avx512vbmi2vlintrin): New headers.
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config/i386/avx512vbmi2intrin.h (_mm512_mask_compress_epi8,
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* config.gcc (avx512vbmi2intrin.h, avx512vbmi2vlintrin): New headers.
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* config/i386/avx512vbmi2intrin.h (_mm512_mask_compress_epi8,
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_mm512_maskz_compress_epi8, _mm512_mask_compressstoreu_epi8,
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_mm512_mask_compress_epi16, _mm512_maskz_compress_epi16,
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_mm512_mask_compressstoreu_epi16): New.
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config/i386/avx512vbmi2vlintrin.h (_mm_mask_compress_epi8,
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* config/i386/avx512vbmi2vlintrin.h (_mm_mask_compress_epi8,
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_mm_maskz_compress_epi8, _mm256_mask_compressstoreu_epi16,
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_mm_mask_compress_epi16, _mm_maskz_compress_epi16,
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_mm256_mask_compress_epi16, _mm256_maskz_compress_epi16,
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_mm_mask_compressstoreu_epi8, _mm_mask_compressstoreu_epi16,
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_mm256_mask_compress_epi8, _mm256_maskz_compress_epi8,
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_mm256_mask_compressstoreu_epi8): New.
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config/i386/i386-builtin-types.def (VOID_FTYPE_PV64QI_V64QI_UDI,
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* config/i386/i386-builtin-types.def (VOID_FTYPE_PV64QI_V64QI_UDI,
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VOID_FTYPE_PV32HI_V32HI_USI, VOID_FTYPE_PV32QI_V32QI_USI,
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VOID_FTYPE_PV16QI_V16QI_UHI, VOID_FTYPE_PV16HI_V16HI_UHI,
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VOID_FTYPE_PV8HI_V8HI_UQI): New types.
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config/i386/i386-builtin.def (__builtin_ia32_compressqi512_mask,
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* config/i386/i386-builtin.def (__builtin_ia32_compressqi512_mask,
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__builtin_ia32_compresshi512_mask, __builtin_ia32_compressqi256_mask,
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__builtin_ia32_compressqi128_mask, __builtin_ia32_compresshi256_mask,
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__builtin_ia32_compresshi128_mask,
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@ -119,12 +146,12 @@
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__builtin_ia32_compressstoreuqi128_mask,
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__builtin_ia32_compressstoreuhi256_mask,
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__builtin_ia32_compressstoreuhi128_mask): New builtins.
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config/i386/i386.c (ix86_init_mmx_sse_builtins): Create special args
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* config/i386/i386.c (ix86_init_mmx_sse_builtins): Create special args
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array for flags2.
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(ix86_expand_special_args_builtin): Handle new types.
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(s4fma_expand): Handle new builtin array.
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config/i386/immintrin.h: Include new headers.
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config/i386/sse.md (VI12_AVX512VLBW): New iterator.
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* config/i386/immintrin.h: Include new headers.
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* config/i386/sse.md (VI12_AVX512VLBW): New iterator.
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(compress<mode>_mask, compressstore<mode>_mask): New patterns.
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2017-11-23 Jakub Jelinek <jakub@redhat.com>
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@ -1438,7 +1465,7 @@
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* config/i386/i386.opt (mavx512vbmi2): New option.
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* doc/invoke.texi: Add new option.
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[2017-11-16 Julia Koval <julia.koval@intel.com>
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2017-11-16 Julia Koval <julia.koval@intel.com>
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* config/i386/gfniintrin.h (_mm_gf2p8mul_epi8, _mm256_gf2p8mul_epi8,
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_mm_mask_gf2p8mul_epi8, _mm_maskz_gf2p8mul_epi8,
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@ -631,7 +631,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \
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bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
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core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
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sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \
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skylake-avx512 x86-64 native"
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skylake-avx512 cannonlake x86-64 native"
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# Additional x86 processors supported by --with-cpu=. Each processor
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# MUST be separated by exactly one space.
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@ -793,24 +793,38 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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/* Kaby Lake. */
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cpu = "skylake";
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break;
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case 0x55:
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/* Skylake with AVX-512. */
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cpu = "skylake-avx512";
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break;
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case 0x57:
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/* Knights Landing. */
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cpu = "knl";
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break;
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case 0x66:
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/* Cannon Lake. */
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cpu = "cannonlake";
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break;
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case 0x85:
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/* Knights Mill. */
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/* Knights Mill. */
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cpu = "knm";
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break;
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default:
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if (arch)
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{
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/* This is unknown family 0x6 CPU. */
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/* Assume Knights Landing. */
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if (has_avx512f)
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cpu = "knl";
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/* Assume Knights Mill */
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/* Assume Cannon Lake. */
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if (has_avx512vbmi)
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cpu = "cannonlake";
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/* Assume Knights Mill. */
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else if (has_avx5124vnniw)
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cpu = "knm";
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/* Assume Knights Landing. */
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else if (has_avx512er)
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cpu = "knl";
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/* Assume Skylake with AVX-512. */
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else if (has_avx512f)
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cpu = "skylake-avx512";
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/* Assume Skylake. */
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else if (has_clflushopt)
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cpu = "skylake";
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@ -184,6 +184,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__skylake_avx512");
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def_or_undef (parse_in, "__skylake_avx512__");
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break;
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case PROCESSOR_CANNONLAKE:
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def_or_undef (parse_in, "__cannonlake");
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def_or_undef (parse_in, "__cannonlake__");
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break;
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/* use PROCESSOR_max to not set/unset the arch macro. */
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case PROCESSOR_max:
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break;
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@ -302,6 +306,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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case PROCESSOR_SKYLAKE_AVX512:
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def_or_undef (parse_in, "__tune_skylake_avx512__");
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break;
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case PROCESSOR_CANNONLAKE:
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def_or_undef (parse_in, "__tune_cannonlake__");
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break;
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case PROCESSOR_LAKEMONT:
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def_or_undef (parse_in, "__tune_lakemont__");
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break;
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@ -142,6 +142,7 @@ const struct processor_costs *ix86_cost = NULL;
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#define m_KNL (1U<<PROCESSOR_KNL)
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#define m_KNM (1U<<PROCESSOR_KNM)
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#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512)
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#define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE)
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#define m_INTEL (1U<<PROCESSOR_INTEL)
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#define m_GEODE (1U<<PROCESSOR_GEODE)
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@ -853,7 +854,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
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{"silvermont", &slm_cost, 16, 15, 16, 7, 16},
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{"knl", &slm_cost, 16, 15, 16, 7, 16},
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{"knm", &slm_cost, 16, 15, 16, 7, 16},
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{"skylake-avx512", &core_cost, 16, 10, 16, 10, 16},
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{"skylake-avx512", &skylake_cost, 16, 10, 16, 10, 16},
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{"cannonlake", &core_cost, 16, 10, 16, 10, 16},
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{"intel", &intel_cost, 16, 15, 16, 7, 16},
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{"geode", &geode_cost, 0, 0, 0, 0, 0},
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{"k6", &k6_cost, 32, 7, 32, 7, 32},
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@ -3444,6 +3446,8 @@ ix86_option_override_internal (bool main_args_p,
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#define PTA_SKYLAKE_AVX512 \
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(PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \
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| PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU)
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#define PTA_CANNONLAKE \
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(PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA | PTA_CLWB)
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#define PTA_KNL \
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(PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
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#define PTA_BONNELL \
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@ -3516,7 +3520,9 @@ ix86_option_override_internal (bool main_args_p,
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{"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
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{"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
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{"skylake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_SKYLAKE},
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{"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_SKYLAKE_AVX512},
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{"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
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PTA_SKYLAKE_AVX512},
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{"cannonlake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_CANNONLAKE},
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{"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
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{"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
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{"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
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@ -31230,7 +31236,9 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
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break;
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case PROCESSOR_HASWELL:
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case PROCESSOR_SKYLAKE_AVX512:
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if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)
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if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VBMI)
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arg_str = "cannonlake";
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else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)
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arg_str = "skylake-avx512";
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else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_XSAVES)
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arg_str = "skylake";
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@ -31952,7 +31960,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
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M_INTEL_COREI7_HASWELL,
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M_INTEL_COREI7_BROADWELL,
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M_INTEL_COREI7_SKYLAKE,
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M_INTEL_COREI7_SKYLAKE_AVX512
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M_INTEL_COREI7_SKYLAKE_AVX512,
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M_INTEL_COREI7_CANNONLAKE
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};
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static struct _arch_names_table
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@ -31976,6 +31985,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
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{"broadwell", M_INTEL_COREI7_BROADWELL},
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{"skylake", M_INTEL_COREI7_SKYLAKE},
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{"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512},
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{"cannonlake", M_INTEL_COREI7_CANNONLAKE},
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{"bonnell", M_INTEL_BONNELL},
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{"silvermont", M_INTEL_SILVERMONT},
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{"knl", M_INTEL_KNL},
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|
|
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|
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@ -374,6 +374,7 @@ extern const struct processor_costs ix86_size_cost;
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#define TARGET_KNL (ix86_tune == PROCESSOR_KNL)
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#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
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#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
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#define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
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#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
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#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
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#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
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|
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@ -2255,6 +2256,7 @@ enum processor_type
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PROCESSOR_KNL,
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PROCESSOR_KNM,
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PROCESSOR_SKYLAKE_AVX512,
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PROCESSOR_CANNONLAKE,
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PROCESSOR_INTEL,
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PROCESSOR_GEODE,
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PROCESSOR_K6,
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|
|
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|
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@ -1515,6 +1515,95 @@ struct processor_costs znver1_cost = {
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COSTS_N_INSNS (2), /* cond_not_taken_branch_cost. */
|
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};
|
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|
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/* skylake_cost should produce code tuned for Skylake familly of CPUs. */
|
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static stringop_algs skylake_memcpy[2] = {
|
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{libcall, {{1024, rep_prefix_4_byte, true}, {-1, libcall, false}}},
|
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{libcall, {{16, loop, false}, {512, rep_prefix_8_byte, false},
|
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{-1, libcall, false}}}};
|
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|
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static stringop_algs skylake_memset[2] = {
|
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{libcall, {{6, loop_1_byte, true},
|
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{24, loop, true},
|
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{8192, rep_prefix_4_byte, true},
|
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{-1, libcall, false}}},
|
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{libcall, {{24, loop, true}, {512, rep_prefix_8_byte, false},
|
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{-1, libcall, false}}}};
|
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|
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static const
|
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struct processor_costs skylake_cost = {
|
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COSTS_N_INSNS (1), /* cost of an add instruction */
|
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COSTS_N_INSNS (1)+1, /* cost of a lea instruction */
|
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COSTS_N_INSNS (1), /* variable shift costs */
|
||||
COSTS_N_INSNS (1), /* constant shift costs */
|
||||
{COSTS_N_INSNS (3), /* cost of starting multiply for QI */
|
||||
COSTS_N_INSNS (4), /* HI */
|
||||
COSTS_N_INSNS (3), /* SI */
|
||||
COSTS_N_INSNS (4), /* DI */
|
||||
COSTS_N_INSNS (4)}, /* other */
|
||||
0, /* cost of multiply per each bit set */
|
||||
{COSTS_N_INSNS (8), /* cost of a divide/mod for QI */
|
||||
COSTS_N_INSNS (8), /* HI */
|
||||
COSTS_N_INSNS (11), /* SI */
|
||||
COSTS_N_INSNS (76), /* DI */
|
||||
COSTS_N_INSNS (76)}, /* other */
|
||||
COSTS_N_INSNS (1), /* cost of movsx */
|
||||
COSTS_N_INSNS (0), /* cost of movzx */
|
||||
8, /* "large" insn */
|
||||
17, /* MOVE_RATIO */
|
||||
|
||||
6, /* cost for loading QImode using movzbl */
|
||||
{4, 4, 4}, /* cost of loading integer registers
|
||||
in QImode, HImode and SImode.
|
||||
Relative to reg-reg move (2). */
|
||||
{6, 6, 6}, /* cost of storing integer registers */
|
||||
2, /* cost of reg,reg fld/fst */
|
||||
{6, 6, 8}, /* cost of loading fp registers
|
||||
in SFmode, DFmode and XFmode */
|
||||
{6, 6, 10}, /* cost of storing fp registers
|
||||
in SFmode, DFmode and XFmode */
|
||||
2, /* cost of moving MMX register */
|
||||
{6, 6}, /* cost of loading MMX registers
|
||||
in SImode and DImode */
|
||||
{6, 6}, /* cost of storing MMX registers
|
||||
in SImode and DImode */
|
||||
2, 2, 4, /* cost of moving XMM,YMM,ZMM register */
|
||||
{6, 6, 6, 10, 20}, /* cost of loading SSE registers
|
||||
in 32,64,128,256 and 512-bit */
|
||||
{6, 6, 6, 10, 20}, /* cost of unaligned loads. */
|
||||
{8, 8, 8, 8, 16}, /* cost of storing SSE registers
|
||||
in 32,64,128,256 and 512-bit */
|
||||
{8, 8, 8, 8, 16}, /* cost of unaligned stores. */
|
||||
2, 2, /* SSE->integer and integer->SSE moves */
|
||||
20, 8, /* Gather load static, per_elt. */
|
||||
22, 10, /* Gather store static, per_elt. */
|
||||
64, /* size of l1 cache. */
|
||||
512, /* size of l2 cache. */
|
||||
64, /* size of prefetch block */
|
||||
6, /* number of parallel prefetches */
|
||||
3, /* Branch cost */
|
||||
COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
|
||||
COSTS_N_INSNS (4), /* cost of FMUL instruction. */
|
||||
COSTS_N_INSNS (20), /* cost of FDIV instruction. */
|
||||
COSTS_N_INSNS (1), /* cost of FABS instruction. */
|
||||
COSTS_N_INSNS (1), /* cost of FCHS instruction. */
|
||||
COSTS_N_INSNS (20), /* cost of FSQRT instruction. */
|
||||
|
||||
COSTS_N_INSNS (1), /* cost of cheap SSE instruction. */
|
||||
COSTS_N_INSNS (4), /* cost of ADDSS/SD SUBSS/SD insns. */
|
||||
COSTS_N_INSNS (4), /* cost of MULSS instruction. */
|
||||
COSTS_N_INSNS (4), /* cost of MULSD instruction. */
|
||||
COSTS_N_INSNS (4), /* cost of FMA SS instruction. */
|
||||
COSTS_N_INSNS (4), /* cost of FMA SD instruction. */
|
||||
COSTS_N_INSNS (11), /* cost of DIVSS instruction. */
|
||||
COSTS_N_INSNS (14), /* cost of DIVSD instruction. */
|
||||
COSTS_N_INSNS (12), /* cost of SQRTSS instruction. */
|
||||
COSTS_N_INSNS (18), /* cost of SQRTSD instruction. */
|
||||
1, 4, 2, 2, /* reassoc int, fp, vec_int, vec_fp. */
|
||||
skylake_memcpy,
|
||||
skylake_memset,
|
||||
COSTS_N_INSNS (3), /* cond_taken_branch_cost. */
|
||||
COSTS_N_INSNS (1), /* cond_not_taken_branch_cost. */
|
||||
};
|
||||
/* BTVER1 has optimized REP instruction for medium sized blocks, but for
|
||||
very small blocks it is better to use loop. For large blocks, libcall can
|
||||
do nontemporary accesses and beat inline considerably. */
|
||||
|
|
|
|||
|
|
@ -25321,6 +25321,13 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA
|
|||
BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
|
||||
AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
|
||||
|
||||
@item cannonlake
|
||||
Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
|
||||
SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
|
||||
RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
|
||||
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
|
||||
AVX512IFMA, SHA, CLWB and UMIP instruction set support.
|
||||
|
||||
@item k6
|
||||
AMD K6 CPU with MMX instruction set support.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2017-11-26 Julia Koval <julia.koval@intel.com>
|
||||
|
||||
* gcc.target/i386/funcspec-56.inc: Handle new march.
|
||||
* g++.dg/ext/mv16.C: Ditto.
|
||||
|
||||
2017-11-25 Jakub Jelinek <jakub@redhat.com>
|
||||
|
||||
PR rtl-optimization/81553
|
||||
|
|
|
|||
|
|
@ -56,6 +56,10 @@ int __attribute__ ((target("arch=skylake-avx512"))) foo () {
|
|||
return 15;
|
||||
}
|
||||
|
||||
int __attribute__ ((target("arch=cannonlake"))) foo () {
|
||||
return 16;
|
||||
}
|
||||
|
||||
int main ()
|
||||
{
|
||||
int val = foo ();
|
||||
|
|
@ -76,6 +80,8 @@ int main ()
|
|||
assert (val == 14);
|
||||
else if (__builtin_cpu_is ("skylake-avx512"))
|
||||
assert (val == 15);
|
||||
else if (__builtin_cpu_is ("cannonlake"))
|
||||
assert (val == 16);
|
||||
else
|
||||
assert (val == 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -144,6 +144,7 @@ extern void test_arch_core_avx2 (void) __attribute__((__target__("arch=core-avx
|
|||
extern void test_arch_knl (void) __attribute__((__target__("arch=knl")));
|
||||
extern void test_arch_knm (void) __attribute__((__target__("arch=knm")));
|
||||
extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512")));
|
||||
extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake")));
|
||||
extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
|
||||
extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));
|
||||
extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron")));
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2017-11-26 Julia Koval <julia.koval@intel.com>
|
||||
|
||||
* config/i386/cpuinfo.c (get_intel_cpu): Handle cannonlake.
|
||||
* config/i386/cpuinfo.h (processor_subtypes): Add
|
||||
INTEL_COREI7_CANNONLAKE.
|
||||
|
||||
2017-11-20 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
|
||||
|
||||
PR bootstrap/83015
|
||||
|
|
|
|||
|
|
@ -198,6 +198,11 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
|
|||
__cpu_model.__cpu_type = INTEL_COREI7;
|
||||
__cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE_AVX512;
|
||||
break;
|
||||
case 0x66:
|
||||
/* Cannon Lake. */
|
||||
__cpu_model.__cpu_type = INTEL_COREI7;
|
||||
__cpu_model.__cpu_subtype = INTEL_COREI7_CANNONLAKE;
|
||||
break;
|
||||
case 0x17:
|
||||
case 0x1d:
|
||||
/* Penryn. */
|
||||
|
|
|
|||
|
|
@ -69,6 +69,7 @@ enum processor_subtypes
|
|||
INTEL_COREI7_BROADWELL,
|
||||
INTEL_COREI7_SKYLAKE,
|
||||
INTEL_COREI7_SKYLAKE_AVX512,
|
||||
INTEL_COREI7_CANNONLAKE,
|
||||
CPU_SUBTYPE_MAX
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue