thumb2.md (thumb2_notsi_shiftsi, [...]): Delete.
* config/arm/thumb2.md (thumb2_notsi_shiftsi, thumbsi_notsi_shiftsi_compare0, thumb2_not_shiftsi_compare0_scratch, thumb2_cmpsi_shiftsi, thumb2_cmpsi_shiftsi_swp, thumb2_arith_shiftsi, thumb2_arith_shiftsi splitter, thumb2_arith_shiftsi_compare0, thumb2_arith_shiftsi_compare0_scratch, thumb2_sub_shiftsi, thumb2_sub_shiftsi_compare0, thumb2_sub_shiftsi_compare0_scratch, thumb2_iorsi3): Delete. (orsi_notsi_si): No longer a named pattern. (orsi_not_shiftsi_si): Renamed from thumb_orsi_not_shiftsi_si. * config/arm/predicates.md (shift_amount_operand): New. (mult_operator): New. * config/arm/arm.md (attr arch, attr arch_enabled, attr insn_enabled, attr enabled): New. (iorsi3_insn): Renamed from arm_iorsi3. Handle a new alternative if arch matches t2. (not_shiftsi): Renamed from arm_notsi_shiftsi. Handle Thumb2 variant. (not_shiftsi_compare0): Likewise, renamed from arm_notsi_shiftsi_compare0. (not_shiftsi_compare0_scratch): Likweise, renamed from arm_notsi_shiftsi_compare0_scratch. (cmpsi_shiftsi): Likewise, renamed from arm_cmpsi_shiftsi. (cmpsi_shiftsi_swp): Likewise, renamed from arm_cmpsi_shiftsi_swp. (arith_shiftsi): Handle Thumb2 variant. Set insn_enabled attribute so that the register alternative is disabled when the shift_operator is MULT. Use "M" as the constraint for constants. (arith_shiftsi splitter): Enable for TARGET_32BIT. (arith_shiftsi_compare0): Handle Thumb2 variant. Use "M" as the constraint for constants. (arith_shiftsi_compare0_scratch): Likewise. (sub_shiftsi, sub_shiftsi_compare0, sub_shiftsi_compare0_scratch): Handle Thumb2 alternative. From-SVN: r163281
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
c878765bbf
commit
c29e2982e4
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@ -1,3 +1,37 @@
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2010-08-16 Bernd Schmidt <bernds@codesourcery.com>
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* config/arm/thumb2.md (thumb2_notsi_shiftsi,
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thumbsi_notsi_shiftsi_compare0, thumb2_not_shiftsi_compare0_scratch,
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thumb2_cmpsi_shiftsi, thumb2_cmpsi_shiftsi_swp, thumb2_arith_shiftsi,
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thumb2_arith_shiftsi splitter, thumb2_arith_shiftsi_compare0,
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thumb2_arith_shiftsi_compare0_scratch, thumb2_sub_shiftsi,
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thumb2_sub_shiftsi_compare0, thumb2_sub_shiftsi_compare0_scratch,
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thumb2_iorsi3): Delete.
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(orsi_notsi_si): No longer a named pattern.
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(orsi_not_shiftsi_si): Renamed from thumb_orsi_not_shiftsi_si.
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* config/arm/predicates.md (shift_amount_operand): New.
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(mult_operator): New.
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* config/arm/arm.md (attr arch, attr arch_enabled, attr insn_enabled,
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attr enabled): New.
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(iorsi3_insn): Renamed from arm_iorsi3. Handle a new alternative if
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arch matches t2.
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(not_shiftsi): Renamed from arm_notsi_shiftsi. Handle Thumb2 variant.
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(not_shiftsi_compare0): Likewise, renamed from
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arm_notsi_shiftsi_compare0.
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(not_shiftsi_compare0_scratch): Likweise, renamed from
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arm_notsi_shiftsi_compare0_scratch.
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(cmpsi_shiftsi): Likewise, renamed from arm_cmpsi_shiftsi.
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(cmpsi_shiftsi_swp): Likewise, renamed from arm_cmpsi_shiftsi_swp.
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(arith_shiftsi): Handle Thumb2 variant. Set insn_enabled attribute
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so that the register alternative is disabled when the shift_operator
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is MULT. Use "M" as the constraint for constants.
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(arith_shiftsi splitter): Enable for TARGET_32BIT.
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(arith_shiftsi_compare0): Handle Thumb2 variant. Use "M" as the
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constraint for constants.
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(arith_shiftsi_compare0_scratch): Likewise.
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(sub_shiftsi, sub_shiftsi_compare0, sub_shiftsi_compare0_scratch):
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Handle Thumb2 alternative.
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2010-08-16 Joseph Myers <joseph@codesourcery.com>
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* doc/options.texi (NoDriverArg): Document.
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@ -167,6 +167,59 @@
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; LENGTH of an instruction (in bytes)
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(define_attr "length" "" (const_int 4))
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; The architecture which supports the instruction (or alternative).
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; This can be "a" for ARM, "t" for either of the Thumbs, "32" for
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; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode. "v6"
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; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without
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; arm_arch6. This attribute is used to compute attribute "enabled",
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; use type "any" to enable an alternative in all cases.
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(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6"
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(const_string "any"))
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(define_attr "arch_enabled" "no,yes"
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(cond [(eq_attr "arch" "any")
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(const_string "yes")
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(and (eq_attr "arch" "a")
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(ne (symbol_ref "TARGET_ARM") (const_int 0)))
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(const_string "yes")
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(and (eq_attr "arch" "t")
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(ne (symbol_ref "TARGET_THUMB") (const_int 0)))
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(const_string "yes")
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(and (eq_attr "arch" "t1")
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(ne (symbol_ref "TARGET_THUMB1") (const_int 0)))
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(const_string "yes")
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(and (eq_attr "arch" "t2")
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(ne (symbol_ref "TARGET_THUMB2") (const_int 0)))
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(const_string "yes")
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(and (eq_attr "arch" "32")
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(ne (symbol_ref "TARGET_32BIT") (const_int 0)))
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(const_string "yes")
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(and (eq_attr "arch" "v6")
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(ne (symbol_ref "(TARGET_32BIT && arm_arch6)") (const_int 0)))
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(const_string "yes")
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(and (eq_attr "arch" "nov6")
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(ne (symbol_ref "(TARGET_32BIT && !arm_arch6)") (const_int 0)))
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(const_string "yes")]
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(const_string "no")))
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; Allows an insn to disable certain alternatives for reasons other than
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; arch support.
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(define_attr "insn_enabled" "no,yes"
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(const_string "yes"))
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; Enable all alternatives that are both arch_enabled and insn_enabled.
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(define_attr "enabled" "no,yes"
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(if_then_else (eq_attr "insn_enabled" "yes")
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(attr "arch_enabled")
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(const_string "no")))
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; POOL_RANGE is how far away from a constant pool entry that this insn
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; can be placed. If the distance is zero, then this insn will never
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; reference the pool.
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@ -2697,26 +2750,28 @@
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"
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)
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(define_insn_and_split "*arm_iorsi3"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(ior:SI (match_operand:SI 1 "s_register_operand" "r,r")
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(match_operand:SI 2 "reg_or_int_operand" "rI,?n")))]
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"TARGET_ARM"
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(define_insn_and_split "*iorsi3_insn"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
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(ior:SI (match_operand:SI 1 "s_register_operand" "%r,r,r")
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(match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
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"TARGET_32BIT"
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"@
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orr%?\\t%0, %1, %2
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orn%?\\t%0, %1, #%B2
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#"
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"TARGET_ARM
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"TARGET_32BIT
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&& GET_CODE (operands[2]) == CONST_INT
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&& !const_ok_for_arm (INTVAL (operands[2]))"
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&& !(const_ok_for_arm (INTVAL (operands[2]))
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|| (TARGET_THUMB2 && const_ok_for_arm (~INTVAL (operands[2]))))"
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[(clobber (const_int 0))]
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"
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{
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arm_split_constant (IOR, SImode, curr_insn,
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INTVAL (operands[2]), operands[0], operands[1], 0);
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DONE;
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"
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[(set_attr "length" "4,16")
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(set_attr "predicable" "yes")]
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)
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}
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[(set_attr "length" "4,4,16")
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(set_attr "arch" "32,t2,32")
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(set_attr "predicable" "yes")])
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(define_insn "*thumb1_iorsi3_insn"
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[(set (match_operand:SI 0 "register_operand" "=l")
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@ -3484,52 +3539,48 @@
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(set_attr "shift" "1")]
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)
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(define_insn "*arm_notsi_shiftsi"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(define_insn "*not_shiftsi"
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[(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(not:SI (match_operator:SI 3 "shift_operator"
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[(match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "arm_rhs_operand" "rM")])))]
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"TARGET_ARM"
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[(match_operand:SI 1 "s_register_operand" "r,r")
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(match_operand:SI 2 "shift_amount_operand" "M,rM")])))]
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"TARGET_32BIT"
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"mvn%?\\t%0, %1%S3"
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[(set_attr "predicable" "yes")
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(set_attr "shift" "1")
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(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
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(const_string "alu_shift")
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(const_string "alu_shift_reg")))]
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)
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(set_attr "arch" "32,a")
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(set_attr "type" "alu_shift,alu_shift_reg")])
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(define_insn "*arm_notsi_shiftsi_compare0"
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(define_insn "*not_shiftsi_compare0"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
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[(match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "arm_rhs_operand" "rM")]))
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(const_int 0)))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(compare:CC_NOOV
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(not:SI (match_operator:SI 3 "shift_operator"
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[(match_operand:SI 1 "s_register_operand" "r,r")
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(match_operand:SI 2 "shift_amount_operand" "M,rM")]))
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(const_int 0)))
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(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
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"TARGET_ARM"
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"TARGET_32BIT"
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"mvn%.\\t%0, %1%S3"
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[(set_attr "conds" "set")
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(set_attr "shift" "1")
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(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
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(const_string "alu_shift")
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(const_string "alu_shift_reg")))]
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)
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(set_attr "arch" "32,a")
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(set_attr "type" "alu_shift,alu_shift_reg")])
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(define_insn "*arm_not_shiftsi_compare0_scratch"
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(define_insn "*not_shiftsi_compare0_scratch"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
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[(match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "arm_rhs_operand" "rM")]))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=r"))]
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"TARGET_ARM"
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(compare:CC_NOOV
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(not:SI (match_operator:SI 3 "shift_operator"
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[(match_operand:SI 1 "s_register_operand" "r,r")
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(match_operand:SI 2 "shift_amount_operand" "M,rM")]))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=r,r"))]
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"TARGET_32BIT"
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"mvn%.\\t%0, %1%S3"
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[(set_attr "conds" "set")
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(set_attr "shift" "1")
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(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
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(const_string "alu_shift")
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(const_string "alu_shift_reg")))]
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)
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(set_attr "arch" "32,a")
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(set_attr "type" "alu_shift,alu_shift_reg")])
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;; We don't really have extzv, but defining this using shifts helps
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;; to reduce register pressure later on.
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@ -7025,35 +7076,31 @@
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[(set_attr "conds" "set")]
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)
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(define_insn "*arm_cmpsi_shiftsi"
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(define_insn "*cmpsi_shiftsi"
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[(set (reg:CC CC_REGNUM)
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(compare:CC (match_operand:SI 0 "s_register_operand" "r")
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(compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
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(match_operator:SI 3 "shift_operator"
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[(match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "arm_rhs_operand" "rM")])))]
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"TARGET_ARM"
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[(match_operand:SI 1 "s_register_operand" "r,r")
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(match_operand:SI 2 "shift_amount_operand" "M,rM")])))]
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"TARGET_32BIT"
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"cmp%?\\t%0, %1%S3"
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[(set_attr "conds" "set")
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(set_attr "shift" "1")
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(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
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(const_string "alu_shift")
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(const_string "alu_shift_reg")))]
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)
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(set_attr "arch" "32,a")
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(set_attr "type" "alu_shift,alu_shift_reg")])
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(define_insn "*arm_cmpsi_shiftsi_swp"
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(define_insn "*cmpsi_shiftsi_swp"
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[(set (reg:CC_SWP CC_REGNUM)
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(compare:CC_SWP (match_operator:SI 3 "shift_operator"
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[(match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "reg_or_int_operand" "rM")])
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(match_operand:SI 0 "s_register_operand" "r")))]
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"TARGET_ARM"
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[(match_operand:SI 1 "s_register_operand" "r,r")
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(match_operand:SI 2 "shift_amount_operand" "M,rM")])
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(match_operand:SI 0 "s_register_operand" "r,r")))]
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"TARGET_32BIT"
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"cmp%?\\t%0, %1%S3"
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[(set_attr "conds" "set")
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(set_attr "shift" "1")
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(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
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(const_string "alu_shift")
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(const_string "alu_shift_reg")))]
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)
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(set_attr "arch" "32,a")
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(set_attr "type" "alu_shift,alu_shift_reg")])
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(define_insn "*arm_cmpsi_negshiftsi_si"
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[(set (reg:CC_Z CC_REGNUM)
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@ -8405,20 +8452,28 @@
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;; Patterns to allow combination of arithmetic, cond code and shifts
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(define_insn "*arith_shiftsi"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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[(set (match_operand:SI 0 "s_register_operand" "=r,r")
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(match_operator:SI 1 "shiftable_operator"
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[(match_operator:SI 3 "shift_operator"
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[(match_operand:SI 4 "s_register_operand" "r")
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(match_operand:SI 5 "reg_or_int_operand" "rI")])
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(match_operand:SI 2 "s_register_operand" "rk")]))]
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"TARGET_ARM"
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[(match_operand:SI 4 "s_register_operand" "r,r")
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(match_operand:SI 5 "shift_amount_operand" "M,r")])
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(match_operand:SI 2 "s_register_operand" "rk,rk")]))]
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"TARGET_32BIT"
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"%i1%?\\t%0, %2, %4%S3"
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[(set_attr "predicable" "yes")
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(set_attr "shift" "4")
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(set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "")
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(const_string "alu_shift")
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(const_string "alu_shift_reg")))]
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)
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(set_attr "arch" "32,a")
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;; We have to make sure to disable the second alternative if
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;; the shift_operator is MULT, since otherwise the insn will
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;; also match a multiply_accumulate pattern and validate_change
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;; will allow a replacement of the constant with a register
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;; despite the checks done in shift_operator.
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(set_attr_alternative "insn_enabled"
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[(const_string "yes")
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(if_then_else
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(match_operand:SI 3 "mult_operator" "")
|
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(const_string "no") (const_string "yes"))])
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(set_attr "type" "alu_shift,alu_shift_reg")])
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|
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(define_split
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[(set (match_operand:SI 0 "s_register_operand" "")
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|
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@ -8430,7 +8485,7 @@
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(match_operand:SI 6 "s_register_operand" "")])
|
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(match_operand:SI 7 "arm_rhs_operand" "")]))
|
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(clobber (match_operand:SI 8 "s_register_operand" ""))]
|
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"TARGET_ARM"
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"TARGET_32BIT"
|
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[(set (match_dup 8)
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(match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
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(match_dup 6)]))
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|
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@ -8440,95 +8495,86 @@
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(define_insn "*arith_shiftsi_compare0"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
|
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[(match_operator:SI 3 "shift_operator"
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[(match_operand:SI 4 "s_register_operand" "r")
|
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(match_operand:SI 5 "reg_or_int_operand" "rI")])
|
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(match_operand:SI 2 "s_register_operand" "r")])
|
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(const_int 0)))
|
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(set (match_operand:SI 0 "s_register_operand" "=r")
|
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(compare:CC_NOOV
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(match_operator:SI 1 "shiftable_operator"
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||||
[(match_operator:SI 3 "shift_operator"
|
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[(match_operand:SI 4 "s_register_operand" "r,r")
|
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(match_operand:SI 5 "shift_amount_operand" "M,r")])
|
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(match_operand:SI 2 "s_register_operand" "r,r")])
|
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(const_int 0)))
|
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(set (match_operand:SI 0 "s_register_operand" "=r,r")
|
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(match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
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(match_dup 2)]))]
|
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"TARGET_ARM"
|
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"TARGET_32BIT"
|
||||
"%i1%.\\t%0, %2, %4%S3"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "4")
|
||||
(set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "")
|
||||
(const_string "alu_shift")
|
||||
(const_string "alu_shift_reg")))]
|
||||
)
|
||||
(set_attr "arch" "32,a")
|
||||
(set_attr "type" "alu_shift,alu_shift_reg")])
|
||||
|
||||
(define_insn "*arith_shiftsi_compare0_scratch"
|
||||
[(set (reg:CC_NOOV CC_REGNUM)
|
||||
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
|
||||
[(match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 4 "s_register_operand" "r")
|
||||
(match_operand:SI 5 "reg_or_int_operand" "rI")])
|
||||
(match_operand:SI 2 "s_register_operand" "r")])
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 0 "=r"))]
|
||||
"TARGET_ARM"
|
||||
(compare:CC_NOOV
|
||||
(match_operator:SI 1 "shiftable_operator"
|
||||
[(match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 4 "s_register_operand" "r,r")
|
||||
(match_operand:SI 5 "shift_amount_operand" "M,r")])
|
||||
(match_operand:SI 2 "s_register_operand" "r,r")])
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 0 "=r,r"))]
|
||||
"TARGET_32BIT"
|
||||
"%i1%.\\t%0, %2, %4%S3"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "4")
|
||||
(set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "")
|
||||
(const_string "alu_shift")
|
||||
(const_string "alu_shift_reg")))]
|
||||
)
|
||||
(set_attr "arch" "32,a")
|
||||
(set_attr "type" "alu_shift,alu_shift_reg")])
|
||||
|
||||
(define_insn "*sub_shiftsi"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
|
||||
(minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
|
||||
(match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "reg_or_int_operand" "rM")])))]
|
||||
"TARGET_ARM"
|
||||
[(match_operand:SI 3 "s_register_operand" "r,r")
|
||||
(match_operand:SI 4 "shift_amount_operand" "M,r")])))]
|
||||
"TARGET_32BIT"
|
||||
"sub%?\\t%0, %1, %3%S2"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "shift" "3")
|
||||
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
|
||||
(const_string "alu_shift")
|
||||
(const_string "alu_shift_reg")))]
|
||||
)
|
||||
(set_attr "arch" "32,a")
|
||||
(set_attr "type" "alu_shift,alu_shift_reg")])
|
||||
|
||||
(define_insn "*sub_shiftsi_compare0"
|
||||
[(set (reg:CC_NOOV CC_REGNUM)
|
||||
(compare:CC_NOOV
|
||||
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
|
||||
(minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
|
||||
(match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "reg_or_int_operand" "rM")]))
|
||||
[(match_operand:SI 3 "s_register_operand" "r,r")
|
||||
(match_operand:SI 4 "shift_amount_operand" "M,rM")]))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
|
||||
(match_dup 4)])))]
|
||||
"TARGET_ARM"
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r,r")
|
||||
(minus:SI (match_dup 1)
|
||||
(match_op_dup 2 [(match_dup 3) (match_dup 4)])))]
|
||||
"TARGET_32BIT"
|
||||
"sub%.\\t%0, %1, %3%S2"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "3")
|
||||
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
|
||||
(const_string "alu_shift")
|
||||
(const_string "alu_shift_reg")))]
|
||||
)
|
||||
(set_attr "arch" "32,a")
|
||||
(set_attr "type" "alu_shift,alu_shift_reg")])
|
||||
|
||||
(define_insn "*sub_shiftsi_compare0_scratch"
|
||||
[(set (reg:CC_NOOV CC_REGNUM)
|
||||
(compare:CC_NOOV
|
||||
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
|
||||
(minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
|
||||
(match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "reg_or_int_operand" "rM")]))
|
||||
[(match_operand:SI 3 "s_register_operand" "r,r")
|
||||
(match_operand:SI 4 "shift_amount_operand" "M,rM")]))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 0 "=r"))]
|
||||
"TARGET_ARM"
|
||||
(clobber (match_scratch:SI 0 "=r,r"))]
|
||||
"TARGET_32BIT"
|
||||
"sub%.\\t%0, %1, %3%S2"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "3")
|
||||
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
|
||||
(const_string "alu_shift")
|
||||
(const_string "alu_shift_reg")))]
|
||||
)
|
||||
|
||||
(set_attr "arch" "32,a")
|
||||
(set_attr "type" "alu_shift,alu_shift_reg")])
|
||||
|
||||
|
||||
(define_insn "*and_scc"
|
||||
|
|
|
|||
|
|
@ -128,6 +128,11 @@
|
|||
(ior (match_operand 0 "arm_rhs_operand")
|
||||
(match_operand 0 "memory_operand")))
|
||||
|
||||
(define_predicate "shift_amount_operand"
|
||||
(ior (and (match_test "TARGET_ARM")
|
||||
(match_operand 0 "s_register_operand"))
|
||||
(match_operand 0 "const_int_operand")))
|
||||
|
||||
(define_predicate "arm_add_operand"
|
||||
(ior (match_operand 0 "arm_rhs_operand")
|
||||
(match_operand 0 "arm_neg_immediate_operand")))
|
||||
|
|
@ -221,6 +226,10 @@
|
|||
(match_code "ashift,ashiftrt,lshiftrt,rotatert"))
|
||||
(match_test "mode == GET_MODE (op)")))
|
||||
|
||||
;; True for MULT, to identify which variant of shift_operator is in use.
|
||||
(define_special_predicate "mult_operator"
|
||||
(match_code "mult"))
|
||||
|
||||
;; True for operators that have 16-bit thumb variants. */
|
||||
(define_special_predicate "thumb_16bit_operator"
|
||||
(match_code "plus,minus,and,ior,xor"))
|
||||
|
|
|
|||
|
|
@ -120,47 +120,6 @@
|
|||
(set_attr "length" "10,10,14")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_notsi_shiftsi"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(not:SI (match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 1 "s_register_operand" "r")
|
||||
(match_operand:SI 2 "const_int_operand" "M")])))]
|
||||
"TARGET_THUMB2"
|
||||
"mvn%?\\t%0, %1%S3"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "shift" "1")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_notsi_shiftsi_compare0"
|
||||
[(set (reg:CC_NOOV CC_REGNUM)
|
||||
(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 1 "s_register_operand" "r")
|
||||
(match_operand:SI 2 "const_int_operand" "M")]))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
|
||||
"TARGET_THUMB2"
|
||||
"mvn%.\\t%0, %1%S3"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "1")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_not_shiftsi_compare0_scratch"
|
||||
[(set (reg:CC_NOOV CC_REGNUM)
|
||||
(compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 1 "s_register_operand" "r")
|
||||
(match_operand:SI 2 "const_int_operand" "M")]))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 0 "=r"))]
|
||||
"TARGET_THUMB2"
|
||||
"mvn%.\\t%0, %1%S3"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "1")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
|
||||
(define_insn "*thumb2_negdi2"
|
||||
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
|
||||
|
|
@ -260,32 +219,6 @@
|
|||
(set_attr "neg_pool_range" "*,*,*,250")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_cmpsi_shiftsi"
|
||||
[(set (reg:CC CC_REGNUM)
|
||||
(compare:CC (match_operand:SI 0 "s_register_operand" "r")
|
||||
(match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 1 "s_register_operand" "r")
|
||||
(match_operand:SI 2 "const_int_operand" "M")])))]
|
||||
"TARGET_THUMB2"
|
||||
"cmp%?\\t%0, %1%S3"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "1")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_cmpsi_shiftsi_swp"
|
||||
[(set (reg:CC_SWP CC_REGNUM)
|
||||
(compare:CC_SWP (match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 1 "s_register_operand" "r")
|
||||
(match_operand:SI 2 "const_int_operand" "M")])
|
||||
(match_operand:SI 0 "s_register_operand" "r")))]
|
||||
"TARGET_THUMB2"
|
||||
"cmp%?\\t%0, %1%S3"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "1")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_cmpsi_neg_shiftsi"
|
||||
[(set (reg:CC CC_REGNUM)
|
||||
(compare:CC (match_operand:SI 0 "s_register_operand" "r")
|
||||
|
|
@ -396,122 +329,6 @@
|
|||
;; addresses will have the thumb bit set correctly.
|
||||
|
||||
|
||||
;; Patterns to allow combination of arithmetic, cond code and shifts
|
||||
|
||||
(define_insn "*thumb2_arith_shiftsi"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(match_operator:SI 1 "shiftable_operator"
|
||||
[(match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 4 "s_register_operand" "r")
|
||||
(match_operand:SI 5 "const_int_operand" "M")])
|
||||
(match_operand:SI 2 "s_register_operand" "rk")]))]
|
||||
"TARGET_THUMB2"
|
||||
"%i1%?\\t%0, %2, %4%S3"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "shift" "4")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
;; ??? What does this splitter do? Copied from the ARM version
|
||||
(define_split
|
||||
[(set (match_operand:SI 0 "s_register_operand" "")
|
||||
(match_operator:SI 1 "shiftable_operator"
|
||||
[(match_operator:SI 2 "shiftable_operator"
|
||||
[(match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 4 "s_register_operand" "")
|
||||
(match_operand:SI 5 "const_int_operand" "")])
|
||||
(match_operand:SI 6 "s_register_operand" "")])
|
||||
(match_operand:SI 7 "arm_rhs_operand" "")]))
|
||||
(clobber (match_operand:SI 8 "s_register_operand" ""))]
|
||||
"TARGET_32BIT"
|
||||
[(set (match_dup 8)
|
||||
(match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
|
||||
(match_dup 6)]))
|
||||
(set (match_dup 0)
|
||||
(match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
|
||||
"")
|
||||
|
||||
(define_insn "*thumb2_arith_shiftsi_compare0"
|
||||
[(set (reg:CC_NOOV CC_REGNUM)
|
||||
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
|
||||
[(match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 4 "s_register_operand" "r")
|
||||
(match_operand:SI 5 "const_int_operand" "M")])
|
||||
(match_operand:SI 2 "s_register_operand" "r")])
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
|
||||
(match_dup 2)]))]
|
||||
"TARGET_32BIT"
|
||||
"%i1%.\\t%0, %2, %4%S3"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "4")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_arith_shiftsi_compare0_scratch"
|
||||
[(set (reg:CC_NOOV CC_REGNUM)
|
||||
(compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
|
||||
[(match_operator:SI 3 "shift_operator"
|
||||
[(match_operand:SI 4 "s_register_operand" "r")
|
||||
(match_operand:SI 5 "const_int_operand" "M")])
|
||||
(match_operand:SI 2 "s_register_operand" "r")])
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 0 "=r"))]
|
||||
"TARGET_THUMB2"
|
||||
"%i1%.\\t%0, %2, %4%S3"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "4")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_sub_shiftsi"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
|
||||
(match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_int_operand" "M")])))]
|
||||
"TARGET_THUMB2"
|
||||
"sub%?\\t%0, %1, %3%S2"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "shift" "3")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_sub_shiftsi_compare0"
|
||||
[(set (reg:CC_NOOV CC_REGNUM)
|
||||
(compare:CC_NOOV
|
||||
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
|
||||
(match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_int_operand" "M")]))
|
||||
(const_int 0)))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
|
||||
(match_dup 4)])))]
|
||||
"TARGET_THUMB2"
|
||||
"sub%.\\t%0, %1, %3%S2"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "3")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_sub_shiftsi_compare0_scratch"
|
||||
[(set (reg:CC_NOOV CC_REGNUM)
|
||||
(compare:CC_NOOV
|
||||
(minus:SI (match_operand:SI 1 "s_register_operand" "r")
|
||||
(match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_int_operand" "M")]))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:SI 0 "=r"))]
|
||||
"TARGET_THUMB2"
|
||||
"sub%.\\t%0, %1, %3%S2"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "shift" "3")
|
||||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_and_scc"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(and:SI (match_operator:SI 1 "arm_comparison_operator"
|
||||
|
|
@ -1365,7 +1182,7 @@
|
|||
(set_attr "length" "2")]
|
||||
)
|
||||
|
||||
(define_insn "orsi_notsi_si"
|
||||
(define_insn "*orsi_notsi_si"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
|
||||
(match_operand:SI 1 "s_register_operand" "r")))]
|
||||
|
|
@ -1374,7 +1191,7 @@
|
|||
[(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb_orsi_not_shiftsi_si"
|
||||
(define_insn "*orsi_not_shiftsi_si"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(ior:SI (not:SI (match_operator:SI 4 "shift_operator"
|
||||
[(match_operand:SI 2 "s_register_operand" "r")
|
||||
|
|
@ -1387,29 +1204,6 @@
|
|||
(set_attr "type" "alu_shift")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_iorsi3"
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
|
||||
(ior:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
|
||||
(match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
|
||||
"TARGET_THUMB2"
|
||||
"@
|
||||
orr%?\\t%0, %1, %2
|
||||
orn%?\\t%0, %1, #%B2
|
||||
#"
|
||||
"TARGET_THUMB2
|
||||
&& GET_CODE (operands[2]) == CONST_INT
|
||||
&& !(const_ok_for_arm (INTVAL (operands[2]))
|
||||
|| const_ok_for_arm (~INTVAL (operands[2])))"
|
||||
[(clobber (const_int 0))]
|
||||
"
|
||||
arm_split_constant (IOR, SImode, curr_insn,
|
||||
INTVAL (operands[2]), operands[0], operands[1], 0);
|
||||
DONE;
|
||||
"
|
||||
[(set_attr "length" "4,4,16")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_peephole2
|
||||
[(set (match_operand:CC_NOOV 0 "cc_register" "")
|
||||
(compare:CC_NOOV (zero_extract:SI
|
||||
|
|
|
|||
Loading…
Reference in New Issue