Patch from Gavin to fix mips16 prologue/epilogue bugs.
* mips/mips.c (mips_expand_prologue,mips_expand_epilogue): Change mode of registers used to add/sub from hard_frame_pointer_rtx from word_mode to Pmode. From-SVN: r17511
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@ -1,3 +1,9 @@
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Tue Jan 27 17:21:09 1998 Gavin Koch (gavin@cygnus.com)
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* mips/mips.c (mips_expand_prologue,mips_expand_epilogue):
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Change mode of registers used to add/sub from
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hard_frame_pointer_rtx from word_mode to Pmode.
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Tue Jan 27 11:02:04 1998 Nick Clifton <nickc@cygnus.com>
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* v850.h (ASM_OUTPUT_ALIGNED_BSS): Use
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@ -174,7 +180,7 @@ Fri Jan 23 00:27:23 1998 John Carr <jfc@mit.edu>
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* toplev.c (get_run_time): Call sysconf(_SC_CLK_TCK), when available,
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to get clock rate.
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Fri Jan 23 00:19:36 1998 Gavin Kock (gavin@cygnus.com)
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Fri Jan 23 00:19:36 1998 Gavin Koch (gavin@cygnus.com)
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* mips.md (muldi3_internal2): Reverse test for TARGET_MIPS16.
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@ -6502,7 +6502,7 @@ mips_expand_prologue ()
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if (!frame_pointer_needed)
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abort ();
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reg_rtx = gen_rtx (REG, word_mode, 3);
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reg_rtx = gen_rtx (REG, Pmode, 3);
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emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
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emit_move_insn (reg_rtx, tsize_rtx);
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if (TARGET_64BIT)
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@ -6722,7 +6722,7 @@ mips_expand_epilogue ()
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add a register to $sp. */
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if (orig_tsize > 32767)
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{
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rtx g6_rtx = gen_rtx (REG, word_mode, GP_REG_FIRST + 6);
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rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
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emit_move_insn (g6_rtx, GEN_INT (tsize));
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if (TARGET_LONG64)
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