* config/alpha/alpha.c (alpha_emit_set_const_1)
(alpha_emit_set_long_const, alpha_extract_integer) (alpha_legitimate_constant_p, alpha_split_const_mov) (alpha_expand_block_clear, alpha_expand_zap_mask, print_operand): [HOST_BITS_PER_WIDE_INT < 64]: Remove dead code. (alpha_emit_set_const_1): Change "(HOST_WIDE_INT) 1" to HOST_WIDE_INT_1U. * config/alpha/predicates.md (mode_mask_operand): Do not match const_double RTX. [HOST_BITS_PER_WIDE_INT < 64]: Remove dead code. * config/alpha/alpha.md (abstf, *abstf_internal, UNSPEC_ZAP splitter): Change "(HOST_WIDE_INT) 1" to HOST_WIDE_INT_1U. [HOST_BITS_PER_WIDE_INT < 64]: Remove dead code. (*negtf_internal): Use gen_int_mode instead of immed_double_const. From-SVN: r222994
This commit is contained in:
parent
cbddf64c02
commit
c37aa43b98
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@ -1,3 +1,20 @@
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2015-05-11 Uros Bizjak <ubizjak@gmail.com>
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* config/alpha/alpha.c (alpha_emit_set_const_1)
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(alpha_emit_set_long_const, alpha_extract_integer)
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(alpha_legitimate_constant_p, alpha_split_const_mov)
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(alpha_expand_block_clear, alpha_expand_zap_mask, print_operand):
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[HOST_BITS_PER_WIDE_INT < 64]: Remove dead code.
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(alpha_emit_set_const_1): Change "(HOST_WIDE_INT) 1" to
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HOST_WIDE_INT_1U.
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* config/alpha/predicates.md (mode_mask_operand): Do not match
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const_double RTX.
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[HOST_BITS_PER_WIDE_INT < 64]: Remove dead code.
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* config/alpha/alpha.md (abstf, *abstf_internal, UNSPEC_ZAP splitter):
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Change "(HOST_WIDE_INT) 1" to HOST_WIDE_INT_1U.
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[HOST_BITS_PER_WIDE_INT < 64]: Remove dead code.
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(*negtf_internal): Use gen_int_mode instead of immed_double_const.
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2015-05-11 Jakub Jelinek <jakub@redhat.com>
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PR target/65780
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@ -1771,11 +1771,9 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
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rtx temp, insn;
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/* If this is a sign-extended 32-bit constant, we can do this in at most
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three insns, so do it if we have enough insns left. We always have
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a sign-extended 32-bit constant when compiling on a narrow machine. */
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three insns, so do it if we have enough insns left. */
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if (HOST_BITS_PER_WIDE_INT != 64
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|| c >> 31 == -1 || c >> 31 == 0)
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if (c >> 31 == -1 || c >> 31 == 0)
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{
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HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
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HOST_WIDE_INT tmp1 = c - low;
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@ -1917,11 +1915,9 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
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/* Now try high-order zero bits. Here we try the shifted-in bits as
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all zero and all ones. Be careful to avoid shifting outside the
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mode and to avoid shifting outside the host wide int size. */
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/* On narrow hosts, don't shift a 1 into the high bit, since we'll
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confuse the recursive call and set all of the high 32 bits. */
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bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
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- floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64));
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- floor_log2 (c) - 1);
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if (bits > 0)
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for (; bits > 0; bits--)
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{
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@ -1929,7 +1925,7 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
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temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
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if (!temp)
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{
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new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1);
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new_const = (c << bits) | ((HOST_WIDE_INT_1U << bits) - 1);
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temp = alpha_emit_set_const (subtarget, mode, new_const,
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i, no_output);
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}
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@ -1955,7 +1951,7 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
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temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
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if (!temp)
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{
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new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1);
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new_const = (c << bits) | ((HOST_WIDE_INT_1U << bits) - 1);
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temp = alpha_emit_set_const (subtarget, mode, new_const,
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i, no_output);
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}
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@ -1969,7 +1965,6 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
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}
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}
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#if HOST_BITS_PER_WIDE_INT == 64
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/* Finally, see if can load a value into the target that is the same as the
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constant except that all bytes that are 0 are changed to be 0xff. If we
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can, then we can do a ZAPNOT to obtain the desired constant. */
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@ -1996,7 +1991,6 @@ alpha_emit_set_const_1 (rtx target, machine_mode mode,
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target, 0, OPTAB_WIDEN);
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}
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}
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#endif
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return 0;
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}
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@ -2077,7 +2071,7 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
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HOST_WIDE_INT d1, d2, d3, d4;
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/* Decompose the entire word */
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#if HOST_BITS_PER_WIDE_INT >= 64
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gcc_assert (c2 == -(c1 < 0));
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d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
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c1 -= d1;
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@ -2087,17 +2081,6 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
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c1 -= d3;
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d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
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gcc_assert (c1 == d4);
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#else
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d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
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c1 -= d1;
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d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
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gcc_assert (c1 == d2);
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c2 += (d2 < 0);
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d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
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c2 -= d3;
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d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
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gcc_assert (c2 == d4);
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#endif
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/* Construct the high word */
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if (d4)
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@ -2138,15 +2121,10 @@ alpha_extract_integer (rtx x, HOST_WIDE_INT *p0, HOST_WIDE_INT *p1)
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i0 = INTVAL (x);
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i1 = -(i0 < 0);
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}
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else if (HOST_BITS_PER_WIDE_INT >= 64)
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{
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i0 = CONST_DOUBLE_LOW (x);
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i1 = -(i0 < 0);
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}
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else
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{
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i0 = CONST_DOUBLE_LOW (x);
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i1 = CONST_DOUBLE_HIGH (x);
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i1 = -(i0 < 0);
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}
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*p0 = i0;
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@ -2206,9 +2184,7 @@ alpha_legitimate_constant_p (machine_mode mode, rtx x)
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if (TARGET_BUILD_CONSTANTS)
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return true;
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alpha_extract_integer (x, &i0, &i1);
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if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == (-i0 < 0))
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return alpha_emit_set_const_1 (x, mode, i0, 3, true) != NULL;
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return false;
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return alpha_emit_set_const_1 (x, mode, i0, 3, true) != NULL;
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default:
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return false;
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@ -2226,8 +2202,7 @@ alpha_split_const_mov (machine_mode mode, rtx *operands)
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alpha_extract_integer (operands[1], &i0, &i1);
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if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
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temp = alpha_emit_set_const (operands[0], mode, i0, 3, false);
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temp = alpha_emit_set_const (operands[0], mode, i0, 3, false);
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if (!temp && TARGET_BUILD_CONSTANTS)
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temp = alpha_emit_set_long_const (operands[0], i0, i1);
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@ -4099,7 +4074,6 @@ alpha_expand_block_clear (rtx operands[])
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if (alignofs > 0)
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{
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#if HOST_BITS_PER_WIDE_INT >= 64
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/* Given that alignofs is bounded by align, the only time BWX could
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generate three stores is for a 7 byte fill. Prefer two individual
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stores over a load/mask/store sequence. */
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@ -4134,7 +4108,6 @@ alpha_expand_block_clear (rtx operands[])
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emit_move_insn (mem, tmp);
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}
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#endif
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if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
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{
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@ -4246,7 +4219,6 @@ alpha_expand_block_clear (rtx operands[])
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/* Next clean up any trailing pieces. */
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#if HOST_BITS_PER_WIDE_INT >= 64
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/* Count the number of bits in BYTES for which aligned stores could
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be emitted. */
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words = 0;
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@ -4291,7 +4263,6 @@ alpha_expand_block_clear (rtx operands[])
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return 1;
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}
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}
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#endif
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if (!TARGET_BWX && bytes >= 4)
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{
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@ -4336,43 +4307,16 @@ alpha_expand_zap_mask (HOST_WIDE_INT value)
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{
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rtx result;
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int i;
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HOST_WIDE_INT mask = 0;
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if (HOST_BITS_PER_WIDE_INT >= 64)
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for (i = 7; i >= 0; --i)
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{
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HOST_WIDE_INT mask = 0;
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for (i = 7; i >= 0; --i)
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{
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mask <<= 8;
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if (!((value >> i) & 1))
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mask |= 0xff;
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}
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result = gen_int_mode (mask, DImode);
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}
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else
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{
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HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
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gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
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for (i = 7; i >= 4; --i)
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{
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mask_hi <<= 8;
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if (!((value >> i) & 1))
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mask_hi |= 0xff;
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}
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for (i = 3; i >= 0; --i)
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{
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mask_lo <<= 8;
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if (!((value >> i) & 1))
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mask_lo |= 0xff;
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}
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result = immed_double_const (mask_lo, mask_hi, DImode);
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mask <<= 8;
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if (!((value >> i) & 1))
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mask |= 0xff;
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}
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result = gen_int_mode (mask, DImode);
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return result;
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}
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@ -5288,7 +5232,7 @@ print_operand (FILE *file, rtx x, int code)
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if (!CONST_INT_P (x))
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output_operand_lossage ("invalid %%P value");
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, HOST_WIDE_INT_1 << INTVAL (x));
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break;
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case 'h':
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@ -5385,14 +5329,7 @@ print_operand (FILE *file, rtx x, int code)
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break;
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}
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}
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else if (HOST_BITS_PER_WIDE_INT == 32
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&& GET_CODE (x) == CONST_DOUBLE
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&& CONST_DOUBLE_LOW (x) == 0xffffffff
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&& CONST_DOUBLE_HIGH (x) == 0)
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{
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fputc ('l', file);
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break;
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}
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output_operand_lossage ("invalid %%U value");
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break;
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@ -6788,13 +6725,6 @@ alpha_expand_builtin (tree exp, rtx target,
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return const0_rtx;
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}
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/* Several bits below assume HWI >= 64 bits. This should be enforced
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by config.gcc. */
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#if HOST_BITS_PER_WIDE_INT < 64
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# error "HOST_WIDE_INT too small"
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#endif
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/* Fold the builtin for the CMPBGE instruction. This is a vector comparison
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with an 8-bit output vector. OPINT contains the integer operands; bit N
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of OP_CONST is set if OPINT[N] is valid. */
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@ -951,7 +951,7 @@
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[(set (match_operand:DI 0 "register_operand")
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(and:DI (match_operand:DI 1 "register_operand")
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(match_operand:DI 2 "const_int_operand")))]
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"HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
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"! and_operand (operands[2], DImode)"
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[(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
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(set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
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{
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@ -1508,17 +1508,14 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "mul8_operand" "I"))
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(match_operand:DI 3 "immediate_operand" "i")))]
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"HOST_BITS_PER_WIDE_INT == 64
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&& CONST_INT_P (operands[3])
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&& (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
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(match_operand:DI 3 "const_int_operand" "i")))]
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"((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
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== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
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|| ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
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== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
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|| ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
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== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
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|| ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
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== (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
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|| ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
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== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))"
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{
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#if HOST_BITS_PER_WIDE_INT == 64
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if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
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== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
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return "insbl %1,%s2,%0";
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@ -1528,7 +1525,7 @@
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if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
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== (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
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return "insll %1,%s2,%0";
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#endif
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gcc_unreachable ();
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}
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[(set_attr "type" "shift")])
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@ -1619,13 +1616,7 @@
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(abs:TF (match_operand:TF 1 "reg_or_0_operand")))
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(use (match_dup 2))])]
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"TARGET_HAS_XFLOATING_LIBS"
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{
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#if HOST_BITS_PER_WIDE_INT >= 64
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operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
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#else
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operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
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#endif
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})
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"operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));")
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(define_insn_and_split "*abstf_internal"
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[(set (match_operand:TF 0 "register_operand" "=r")
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@ -1649,13 +1640,7 @@
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(neg:TF (match_operand:TF 1 "reg_or_0_operand")))
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(use (match_dup 2))])]
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"TARGET_HAS_XFLOATING_LIBS"
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{
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#if HOST_BITS_PER_WIDE_INT >= 64
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operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
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#else
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operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
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#endif
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})
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"operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));")
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(define_insn_and_split "*negtf_internal"
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[(set (match_operand:TF 0 "register_operand" "=r")
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@ -5440,7 +5425,7 @@
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(match_operand:DI 2 "reg_or_8bit_operand")]
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""
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{
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rtx mask = immed_double_const (0xffffffff, 0, DImode);
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rtx mask = gen_int_mode (0xffffffff, DImode);
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emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2]));
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DONE;
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})
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@ -5542,16 +5527,8 @@
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[(const_int 0)]
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{
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rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
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if (HOST_BITS_PER_WIDE_INT >= 64 || CONST_INT_P (mask))
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operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
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else
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{
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HOST_WIDE_INT c_lo = INTVAL (operands[1]);
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HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
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operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
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c_hi & CONST_DOUBLE_HIGH (mask),
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DImode);
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}
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operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
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emit_move_insn (operands[0], operands[1]);
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DONE;
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})
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@ -110,26 +110,19 @@
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;; Return 1 if OP is a constant that is a mask of ones of width of an
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;; integral machine mode not larger than DImode.
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(define_predicate "mode_mask_operand"
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(match_code "const_int,const_double")
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(match_code "const_int")
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{
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if (CONST_INT_P (op))
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{
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HOST_WIDE_INT value = INTVAL (op);
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HOST_WIDE_INT value = INTVAL (op);
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if (value == 0xff)
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return 1;
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if (value == 0xffff)
|
||||
return 1;
|
||||
if (value == 0xffffffff)
|
||||
return 1;
|
||||
if (value == -1)
|
||||
return 1;
|
||||
|
||||
if (value == 0xff)
|
||||
return 1;
|
||||
if (value == 0xffff)
|
||||
return 1;
|
||||
if (value == 0xffffffff)
|
||||
return 1;
|
||||
if (value == -1)
|
||||
return 1;
|
||||
}
|
||||
else if (HOST_BITS_PER_WIDE_INT == 32 && GET_CODE (op) == CONST_DOUBLE)
|
||||
{
|
||||
if (CONST_DOUBLE_LOW (op) == 0xffffffff && CONST_DOUBLE_HIGH (op) == 0)
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
})
|
||||
|
||||
|
|
Loading…
Reference in New Issue