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rs6000.c (rs6000_expand_vector_init): Remove unused variable "field". 

2014-01-30  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (rs6000_expand_vector_init): Remove
	unused variable "field".
	* config/rs6000/vsx.md (vsx_mergel_<mode>): Add missing DONE.
	(vsx_mergeh_<mode>): Likewise.
	* config/rs6000/altivec.md (altivec_vmrghb): Likewise.
	(altivec_vmrghh): Likewise.
	(altivec_vmrghw): Likewise.
	(altivec_vmrglb): Likewise.
	(altivec_vmrglh): Likewise.
	(altivec_vmrglw): Likewise.
	(altivec_vspltb): Add missing uses.
	(altivec_vsplth): Likewise.
	(altivec_vspltw): Likewise.
	(altivec_vspltsf): Likewise.

From-SVN: r207326
This commit is contained in:
Bill Schmidt 2014-01-30 22:36:13 +00:00 committed by William Schmidt
parent 4bb9c32da1
commit c3e9607310
4 changed files with 37 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
gcc/ChangeLog
View File

@ -1,3 +1,20 @@
2014-01-30 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_expand_vector_init): Remove
unused variable "field".
* config/rs6000/vsx.md (vsx_mergel_<mode>): Add missing DONE.
(vsx_mergeh_<mode>): Likewise.
* config/rs6000/altivec.md (altivec_vmrghb): Likewise.
(altivec_vmrghh): Likewise.
(altivec_vmrghw): Likewise.
(altivec_vmrglb): Likewise.
(altivec_vmrglh): Likewise.
(altivec_vmrglw): Likewise.
(altivec_vspltb): Add missing uses.
(altivec_vsplth): Likewise.
(altivec_vspltw): Likewise.
(altivec_vspltsf): Likewise.
2014-01-30 Jakub Jelinek <jakub@redhat.com>
PR target/59923

30
gcc/config/rs6000/altivec.md
View File

@ -871,6 +871,7 @@
x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));
emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
DONE;
})
(define_insn "*altivec_vmrghb_internal"
@ -930,6 +931,7 @@
x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));
emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
DONE;
})
(define_insn "*altivec_vmrghh_internal"
@ -983,6 +985,7 @@
x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));
emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
DONE;
})
(define_insn "*altivec_vmrghw_internal"
@ -1057,6 +1060,7 @@
x = gen_rtx_VEC_SELECT (V16QImode, x, gen_rtx_PARALLEL (VOIDmode, v));
emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
DONE;
})
(define_insn "*altivec_vmrglb_internal"
@ -1116,6 +1120,7 @@
x = gen_rtx_VEC_SELECT (V8HImode, x, gen_rtx_PARALLEL (VOIDmode, v));
emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
DONE;
})
(define_insn "*altivec_vmrglh_internal"
@ -1169,6 +1174,7 @@
x = gen_rtx_VEC_SELECT (V4SImode, x, gen_rtx_PARALLEL (VOIDmode, v));
emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
DONE;
})
(define_insn "*altivec_vmrglw_internal"
@ -1601,9 +1607,9 @@
[(set_attr "type" "veccomplex")])
(define_expand "altivec_vspltb"
[(match_operand:V16QI 0 "register_operand" "")
(match_operand:V16QI 1 "register_operand" "")
(match_operand:QI 2 "u5bit_cint_operand" "")]
[(use (match_operand:V16QI 0 "register_operand" ""))
(use (match_operand:V16QI 1 "register_operand" ""))
(use (match_operand:QI 2 "u5bit_cint_operand" ""))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -1649,9 +1655,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vsplth"
[(match_operand:V8HI 0 "register_operand" "")
(match_operand:V8HI 1 "register_operand" "")
(match_operand:QI 2 "u5bit_cint_operand" "")]
[(use (match_operand:V8HI 0 "register_operand" ""))
(use (match_operand:V8HI 1 "register_operand" ""))
(use (match_operand:QI 2 "u5bit_cint_operand" ""))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -1697,9 +1703,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vspltw"
[(match_operand:V4SI 0 "register_operand" "")
(match_operand:V4SI 1 "register_operand" "")
(match_operand:QI 2 "u5bit_cint_operand" "")]
[(use (match_operand:V4SI 0 "register_operand" ""))
(use (match_operand:V4SI 1 "register_operand" ""))
(use (match_operand:QI 2 "u5bit_cint_operand" ""))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -1745,9 +1751,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vspltsf"
[(match_operand:V4SF 0 "register_operand" "")
(match_operand:V4SF 1 "register_operand" "")
(match_operand:QI 2 "u5bit_cint_operand" "")]
[(use (match_operand:V4SF 0 "register_operand" ""))
(use (match_operand:V4SF 1 "register_operand" ""))
(use (match_operand:QI 2 "u5bit_cint_operand" ""))]
"TARGET_ALTIVEC"
{
rtvec v;

1
gcc/config/rs6000/rs6000.c
View File

@ -5511,7 +5511,6 @@ rs6000_expand_vector_init (rtx target, rtx vals)
of 64-bit items is not supported on Altivec. */
if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
{
rtx field;
mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
XVECEXP (vals, 0, 0));

2
gcc/config/rs6000/vsx.md
View File

@ -1701,6 +1701,7 @@
x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));
emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
DONE;
})
(define_expand "vsx_mergeh_<mode>"
@ -1726,6 +1727,7 @@
x = gen_rtx_VEC_SELECT (<MODE>mode, x, gen_rtx_PARALLEL (VOIDmode, v));
emit_insn (gen_rtx_SET (VOIDmode, operands[0], x));
DONE;
})
;; V2DF/V2DI splat