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Using gen_int_mode instead of GEN_INT to avoid ICE caused by type promotion.

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2020-07-22  Hongtao Liu  <hongtao.liu@intel.com>

gcc/
	PR target/96262
	* config/i386/i386-expand.c
	(ix86_expand_vec_shift_qihi_constant): Refine.

gcc/testsuite/
	* gcc.target/i386/pr96262-1.c: New test.
This commit is contained in:
liuhongt 2020-07-22 14:37:24 +08:00
parent b46584d783
commit c44c2a3b05
2 changed files with 14 additions and 3 deletions
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6
gcc/config/i386/i386-expand.c
View File

@ -19604,7 +19604,7 @@ bool
ix86_expand_vec_shift_qihi_constant (enum rtx_code code, rtx dest, rtx op1, rtx op2)
{
machine_mode qimode, himode;
unsigned int and_constant, xor_constant;
HOST_WIDE_INT and_constant, xor_constant;
HOST_WIDE_INT shift_amount;
rtx vec_const_and, vec_const_xor;
rtx tmp, op1_subreg;
@ -19679,7 +19679,7 @@ ix86_expand_vec_shift_qihi_constant (enum rtx_code code, rtx dest, rtx op1, rtx
emit_move_insn (dest, simplify_gen_subreg (qimode, tmp, himode, 0));
emit_move_insn (vec_const_and,
ix86_build_const_vector (qimode, true,
GEN_INT (and_constant)));
gen_int_mode (and_constant, QImode)));
emit_insn (gen_and (dest, dest, vec_const_and));
/* For ASHIFTRT, perform extra operation like
@ -19690,7 +19690,7 @@ ix86_expand_vec_shift_qihi_constant (enum rtx_code code, rtx dest, rtx op1, rtx
vec_const_xor = gen_reg_rtx (qimode);
emit_move_insn (vec_const_xor,
ix86_build_const_vector (qimode, true,
GEN_INT (xor_constant)));
gen_int_mode (xor_constant, QImode)));
emit_insn (gen_xor (dest, dest, vec_const_xor));
emit_insn (gen_sub (dest, dest, vec_const_xor));
}

11
gcc/testsuite/gcc.target/i386/pr96262-1.c Normal file
View File

@ -0,0 +1,11 @@
/* PR target/96262 */
/* { dg-do compile } */
/* { dg-options "-mavx512bw -O" } */
typedef char __attribute__ ((__vector_size__ (64))) V;
V
foo (V v)
{
return ~(v << 1);
}