Scheduling revamp:
* sh.md (attribute type): Add types mt_group, fload, pcfload, fpul_gp, mac_gp ftrc_s and cwb. Add / Adjust definitions in individual insn accordingly. (attribute insn_class): Provide default definitions based on type. Remove all insn-specific settings. (various function units): Remove old SH4 scheduling. (branch_zero, dfp_comp, late_fp_use, any_fp_comp, any_int_load): New attributes. Set them where appropriate. (cpu unit FS): Don't define / use. (F3, load_store): New cpu units. (F01): New reservation. (all insn_reservations): Make dependent on sh4 pipeline model. Fix latencies. (nil, reg_mov, freg_mov, sh4_fpul_gp, sh4_call): New insn_reservations. (sh4_mac_gp, fp_arith_ftrc, arith3, arith3b): Likewise. (mt insn_reservation): Use type mt_group. (insn_reservation load_store): Split into sh4_load, sh4_load_si, sh4_fload and sh4_store. (insn_reservation branch_zero and branch): Replace with sh4_branch. (insn_reservation branch_far): Replace with sh4_return. (insn_reservation return_from_exp): Rename to: (sh4_return_from_exp). Change to be just d_lock*5. (insn_reservation lds_to_pr): Rename to: (sh4_lds_to_pr). Change to be just d_lock*2. (insn_reservation ldsmem_to_pr, sts_from_pr): Change to be just d_lock*2. (insn_reservation prload_mem): Rename to: (sh4_prstore_mem). Change to d_lock*2,nothing,memory. (insn_reservation fpscr_store): Rename to: (fpscr_load). Change to d_lock,nothing,F1*3. (insn_reservation fpscr_store_mem): Rename to: (fpscr_load_mem). Change to d_lock,nothing,(F1+memory),F1*2. (insn_reservation multi): Change to d_lock,(d_lock+f1_1),(f1_1|f1_2)*3,F2. (insn_reservation fp_arith): Change to issue,F01,F2. (insn_reservation fp_div: Change to issue,F01+F3,F2+F3,F3*7,F1+F3,F2. (insn_reservation dp_float): Change to issue,F01,F1+F2,F2. (insn_reservation fp_double_arith): Change to issue,F01,F1+F2,fpu*4,F2. (insn_reservation fp_double_cmp): Change to d_lock,(d_lock+F01),F1+F2,F2. (insn_reservation dp_div): Change to issue,F01+F3,F1+F2+F3,F2+F3,F3*16,F1+F3,(fpu+F3)*2,F2. * sh.c (flow_dependent_p, flow_dependent_p_1): New functions. (sh_adjust_cost, SHcompact): Differentiate between different kinds of dependencies. Drop factor of ten for superscalar. Use new instruction types. Add new exception rules. Two small bug fixes: * sh.md (mulhisi3, umulhisi3: Add a REG_EQUAL note. * sh.md (mperm_w): Add DONE. From-SVN: r56601
This commit is contained in:
J"orn Rennecke
Joern Rennecke
parent
f34fc46e79
commit
c49439f112
@ -1,3 +1,56 @@
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Tue Aug 27 14:39:09 2002 J"orn Rennecke <joern.rennecke@superh.com>
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* sh.md (attribute type): Add types mt_group, fload, pcfload, fpul_gp,
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mac_gp ftrc_s and cwb. Add / Adjust definitions in individual insn
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accordingly.
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(attribute insn_class): Provide default definitions based on type.
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Remove all insn-specific settings.
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(various function units): Remove old SH4 scheduling.
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(branch_zero, dfp_comp, late_fp_use, any_fp_comp, any_int_load):
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New attributes. Set them where appropriate.
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(cpu unit FS): Don't define / use.
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(F3, load_store): New cpu units.
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(F01): New reservation.
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(all insn_reservations): Make dependent on sh4 pipeline model.
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Fix latencies.
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(nil, reg_mov, freg_mov, sh4_fpul_gp, sh4_call): New insn_reservations.
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(sh4_mac_gp, fp_arith_ftrc, arith3, arith3b): Likewise.
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(mt insn_reservation): Use type mt_group.
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(insn_reservation load_store): Split into sh4_load, sh4_load_si,
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sh4_fload and sh4_store.
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(insn_reservation branch_zero and branch): Replace with sh4_branch.
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(insn_reservation branch_far): Replace with sh4_return.
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(insn_reservation return_from_exp): Rename to:
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(sh4_return_from_exp). Change to be just d_lock*5.
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(insn_reservation lds_to_pr): Rename to:
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(sh4_lds_to_pr). Change to be just d_lock*2.
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(insn_reservation ldsmem_to_pr, sts_from_pr): Change to be just
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d_lock*2.
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(insn_reservation prload_mem): Rename to:
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(sh4_prstore_mem). Change to d_lock*2,nothing,memory.
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(insn_reservation fpscr_store): Rename to:
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(fpscr_load). Change to d_lock,nothing,F1*3.
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(insn_reservation fpscr_store_mem): Rename to:
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(fpscr_load_mem). Change to d_lock,nothing,(F1+memory),F1*2.
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(insn_reservation multi): Change to
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d_lock,(d_lock+f1_1),(f1_1|f1_2)*3,F2.
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(insn_reservation fp_arith): Change to issue,F01,F2.
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(insn_reservation fp_div: Change to issue,F01+F3,F2+F3,F3*7,F1+F3,F2.
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(insn_reservation dp_float): Change to issue,F01,F1+F2,F2.
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(insn_reservation fp_double_arith): Change to issue,F01,F1+F2,fpu*4,F2.
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(insn_reservation fp_double_cmp): Change to
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d_lock,(d_lock+F01),F1+F2,F2.
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(insn_reservation dp_div): Change to
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issue,F01+F3,F1+F2+F3,F2+F3,F3*16,F1+F3,(fpu+F3)*2,F2.
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* sh.c (flow_dependent_p, flow_dependent_p_1): New functions.
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(sh_adjust_cost, SHcompact): Differentiate between different
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kinds of dependencies. Drop factor of ten for superscalar.
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Use new instruction types. Add new exception rules.
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* sh.md (mulhisi3, umulhisi3: Add a REG_EQUAL note.
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* sh.md (mperm_w): Add DONE.
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2002-08-27 David Edelsohn <edelsohn@gnu.org>
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* longlong.h: Import current PowerPC defintion from GMP-4.1.
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@ -208,6 +208,8 @@ static const char *sh_strip_name_encoding PARAMS ((const char *));
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static void sh_init_builtins PARAMS ((void));
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static void sh_media_init_builtins PARAMS ((void));
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static rtx sh_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
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static int flow_dependent_p PARAMS ((rtx, rtx));
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static void flow_dependent_p_1 PARAMS ((rtx, rtx, void *));
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/* Initialize the GCC target structure. */
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@ -6994,7 +6996,7 @@ sh_adjust_cost (insn, link, dep_insn, cost)
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rtx dep_insn;
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int cost;
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{
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rtx reg;
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rtx reg, use_pat;
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if (TARGET_SHMEDIA)
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{
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@ -7007,49 +7009,119 @@ sh_adjust_cost (insn, link, dep_insn, cost)
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&& get_attr_is_mac_media (dep_insn))
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cost = 1;
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}
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else if (GET_CODE(insn) == CALL_INSN)
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else if (REG_NOTE_KIND (link) == 0)
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{
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enum attr_type dep_type, type;
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if (recog_memoized (insn) < 0
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|| recog_memoized (dep_insn) < 0)
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return;
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dep_type = get_attr_type (dep_insn);
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if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
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cost--;
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if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
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&& (type = get_attr_type (insn)) != TYPE_CALL
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&& type != TYPE_SFUNC)
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cost--;
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/* The only input for a call that is timing-critical is the
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function's address. */
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rtx call = PATTERN (insn);
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if (GET_CODE(insn) == CALL_INSN)
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{
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rtx call = PATTERN (insn);
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if (GET_CODE (call) == PARALLEL)
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call = XVECEXP (call, 0 ,0);
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if (GET_CODE (call) == SET)
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call = SET_SRC (call);
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if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
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&& ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
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cost = 0;
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}
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/* All sfunc calls are parallels with at least four components.
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Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
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else if (GET_CODE (PATTERN (insn)) == PARALLEL
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&& XVECLEN (PATTERN (insn), 0) >= 4
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&& (reg = sfunc_uses_reg (insn)))
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{
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if (GET_CODE (call) == PARALLEL)
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call = XVECEXP (call, 0 ,0);
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if (GET_CODE (call) == SET)
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call = SET_SRC (call);
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if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
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&& ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
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cost = 0;
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}
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/* Likewise, the most timing critical input for an sfuncs call
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is the function address. However, sfuncs typically start
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using their arguments pretty quickly.
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Assume a four cycle delay before they are needed. */
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if (! reg_set_p (reg, dep_insn))
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cost -= TARGET_SUPERSCALAR ? 40 : 4;
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/* All sfunc calls are parallels with at least four components.
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Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
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else if (GET_CODE (PATTERN (insn)) == PARALLEL
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&& XVECLEN (PATTERN (insn), 0) >= 4
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&& (reg = sfunc_uses_reg (insn)))
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{
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if (! reg_set_p (reg, dep_insn))
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cost -= 4;
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}
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/* When the preceding instruction loads the shift amount of
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the following SHAD/SHLD, the latency of the load is increased
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by 1 cycle. */
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else if (TARGET_SH4
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&& get_attr_type (insn) == TYPE_DYN_SHIFT
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&& get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
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&& reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
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XEXP (SET_SRC (single_set(insn)),
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1)))
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cost++;
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/* When an LS group instruction with a latency of less than
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3 cycles is followed by a double-precision floating-point
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instruction, FIPR, or FTRV, the latency of the first
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instruction is increased to 3 cycles. */
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else if (cost < 3
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&& get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
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&& get_attr_dfp_comp (insn) == DFP_COMP_YES)
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cost = 3;
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/* The lsw register of a double-precision computation is ready one
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cycle earlier. */
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else if (reload_completed
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&& get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
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&& (use_pat = single_set (insn))
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&& ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
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SET_SRC (use_pat)))
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cost -= 1;
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if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
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&& get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
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cost -= 1;
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}
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/* Adjust load_si / pcload_si type insns latency. Use the known
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nominal latency and form of the insn to speed up the check. */
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else if (cost == 3
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&& GET_CODE (PATTERN (dep_insn)) == SET
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/* Latency for dmpy type insns is also 3, so check the that
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it's actually a move insn. */
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&& general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))
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/* An anti-dependence penalty of two applies if the first insn is a double
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precision fadd / fsub / fmul. */
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else if (REG_NOTE_KIND (link) == REG_DEP_ANTI
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&& recog_memoized (dep_insn) >= 0
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&& get_attr_type (dep_insn) == TYPE_DFP_ARITH
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/* A lot of alleged anti-flow dependences are fake,
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so check this one is real. */
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&& flow_dependent_p (dep_insn, insn))
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cost = 2;
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else if (cost == 30
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&& GET_CODE (PATTERN (dep_insn)) == SET
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&& GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode)
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cost = 20;
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return cost;
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}
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/* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
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if DEP_INSN is anti-flow dependent on INSN. */
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static int
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flow_dependent_p (insn, dep_insn)
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rtx insn, dep_insn;
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{
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rtx tmp = PATTERN (insn);
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note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
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return tmp == NULL_RTX;
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}
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/* A helper function for flow_dependent_p called through note_stores. */
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static void
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flow_dependent_p_1 (x, pat, data)
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rtx x;
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rtx pat ATTRIBUTE_UNUSED;
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void *data;
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{
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rtx * pinsn = (rtx *) data;
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if (*pinsn && reg_referenced_p (x, *pinsn))
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*pinsn = NULL_RTX;
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}
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/* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
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'special function' patterns (type sfunc) that clobber pr, but that
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do not look like function calls to leaf_function_p. Hence we must
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@ -7060,27 +7132,26 @@ sh_pr_n_sets ()
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return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
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}
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/* This Function Returns non zero if DFA based scheduler
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interface is to be used.At present supported only for
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SH4. */
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/* This Function returns non zero if the DFA based scheduler interface
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is to be used. At present this is supported for the SH4 only. */
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static int
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sh_use_dfa_interface()
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{
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if (TARGET_SH4)
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return 1;
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else
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return 0;
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if (TARGET_HARD_SH4)
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return 1;
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else
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return 0;
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}
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/* This function returns "2" that signifies dual issue
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for SH4 processor.To be used by DFA pipeline description. */
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/* This function returns "2" to indicate dual issue for the SH4
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processor. To be used by the DFA pipeline description. */
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static int
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sh_issue_rate()
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{
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if(TARGET_SH4)
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return 2;
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else
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return 1;
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if (TARGET_SUPERSCALAR)
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return 2;
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else
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return 1;
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}
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/* SHmedia requires registers for branches, so we can't generate new
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