re PR target/54236 ([SH] Improve addc and subc insn utilization)
gcc/ PR target/54236 * config/sh/sh.md (*addc_r_1): Rename to addc_t_r. Remove empty constraints. (*addc_r_t): Add new insn_and_split. gcc/testsuite/ PR target/54236 * gcc.target/sh/pr54236-3.c: New. From-SVN: r210682
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2014-05-21 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/54236
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* config/sh/sh.md (*addc_r_1): Rename to addc_t_r. Remove empty
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constraints.
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(*addc_r_t): Add new insn_and_split.
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2014-05-21 Jakub Jelinek <jakub@redhat.com>
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2014-05-21 Jakub Jelinek <jakub@redhat.com>
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PR middle-end/61252
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PR middle-end/61252
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@ -1830,6 +1830,8 @@
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;; We allow a reg or 0 for one of the operands in order to be able to
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;; We allow a reg or 0 for one of the operands in order to be able to
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;; do 'reg + T' sequences. Reload will load the constant 0 into the reg
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;; do 'reg + T' sequences. Reload will load the constant 0 into the reg
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;; as needed.
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;; as needed.
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;; FIXME: The load of constant 0 should be split out before reload, or else
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;; it will be difficult to hoist or combine the constant load.
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(define_insn "*addc"
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(define_insn "*addc"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
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(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
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(plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
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@ -1898,10 +1900,10 @@
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;; can be scheduled much better since the load of the constant can be
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;; can be scheduled much better since the load of the constant can be
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;; done earlier, before any comparison insns that store the result in
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;; done earlier, before any comparison insns that store the result in
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;; the T bit.
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;; the T bit.
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(define_insn_and_split "*addc_r_1"
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(define_insn_and_split "*addc_t_r"
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[(set (match_operand:SI 0 "arith_reg_dest" "")
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[(set (match_operand:SI 0 "arith_reg_dest")
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(plus:SI (match_operand:SI 1 "t_reg_operand" "")
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(plus:SI (match_operand:SI 1 "t_reg_operand")
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(match_operand:SI 2 "arith_reg_operand" "")))
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(match_operand:SI 2 "arith_reg_operand")))
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(clobber (reg:SI T_REG))]
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(clobber (reg:SI T_REG))]
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"TARGET_SH1"
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"TARGET_SH1"
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"#"
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"#"
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@ -1911,6 +1913,19 @@
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(match_dup 1)))
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(match_dup 1)))
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(clobber (reg:SI T_REG))])])
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(clobber (reg:SI T_REG))])])
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(define_insn_and_split "*addc_r_t"
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[(set (match_operand:SI 0 "arith_reg_dest")
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(plus:SI (match_operand:SI 1 "arith_reg_operand")
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(match_operand:SI 2 "t_reg_operand")))
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(clobber (reg:SI T_REG))]
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"TARGET_SH1"
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"#"
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"&& 1"
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[(parallel [(set (match_dup 0)
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(plus:SI (plus:SI (match_dup 1) (const_int 0))
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(match_dup 2)))
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(clobber (reg:SI T_REG))])])
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;; Use shlr-addc to do 'reg + (reg & 1)'.
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;; Use shlr-addc to do 'reg + (reg & 1)'.
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(define_insn_and_split "*addc_r_lsb"
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(define_insn_and_split "*addc_r_lsb"
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[(set (match_operand:SI 0 "arith_reg_dest")
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[(set (match_operand:SI 0 "arith_reg_dest")
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@ -1,3 +1,8 @@
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2014-05-21 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/54236
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* gcc.target/sh/pr54236-3.c: New.
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2014-05-21 Igor Zamyatin <igor.zamyatin@intel.com>
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2014-05-21 Igor Zamyatin <igor.zamyatin@intel.com>
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PR c++/60189
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PR c++/60189
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@ -0,0 +1,31 @@
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/* Tests to check the utilization of the addc and subc instructions.
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If everything works as expected we won't see any movt instructions in
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these cases. */
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/* { dg-do compile } */
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/* { dg-options "-O1" } */
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/* { dg-skip-if "" { "sh*-*-*" } { "-m5*"} { "" } } */
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/* { dg-final { scan-assembler-times "addc" 1 } } */
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/* { dg-final { scan-assembler-times "subc" 1 } } */
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/* { dg-final { scan-assembler-not "movt" } } */
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int
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test_000 (int* x, unsigned int c)
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{
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/* 1x addc */
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int s = 0;
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unsigned int i;
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for (i = 0; i < c; ++i)
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s += ! (x[i] & 0x3000);
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return s;
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}
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int
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test_001 (int* x, unsigned int c)
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{
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/* 1x subc */
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int s = 0;
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unsigned int i;
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for (i = 0; i < c; ++i)
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s -= ! (x[i] & 0x3000);
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return s;
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}
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