rs6000.c (mask_operand): Rewrite without bit-shifting loop.
* config/rs6000/rs6000.c (mask_operand): Rewrite without bit-shifting loop. (mask64_operand): Likewise. (rldic_operand): Delete. (includes_lshift64_p): Delete. (includes_rldic_lshift_p): New function. (includes_rldicr_lshift_p): New function. (print_operand): Don't call rldic_operand in case 'W'. * config/rs6000/rs6000-protos.h (rldic_operand): Remove. (includes_lshift64_p): Remove. (includes_rldic_lshift_p): Declare. (includes_rldicr_lshift_p): Declare. * config/rs6000/rs6000.h (PREDICATE_CODES): Remove rldic_operand. * config/rs6000/rs6000.md <ashldi3_internal 64 bit patterns>: Replace match_operand rldic_operand predicate with const_int_operand. Replace includes_lshift64_p condition with includes_rldic_lshift_p. <ashldi3_internal 64 bit rldicr patterns>: New. From-SVN: r45192
This commit is contained in:
Alan Modra
Alan Modra
parent
c34cce4404
commit
c50594233b
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@ -1,3 +1,24 @@
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2001-08-27 Alan Modra <amodra@bigpond.net.au>
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* config/rs6000/rs6000.c (mask_operand): Rewrite without
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bit-shifting loop.
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(mask64_operand): Likewise.
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(rldic_operand): Delete.
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(includes_lshift64_p): Delete.
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(includes_rldic_lshift_p): New function.
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(includes_rldicr_lshift_p): New function.
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(print_operand): Don't call rldic_operand in case 'W'.
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* config/rs6000/rs6000-protos.h (rldic_operand): Remove.
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(includes_lshift64_p): Remove.
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(includes_rldic_lshift_p): Declare.
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(includes_rldicr_lshift_p): Declare.
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* config/rs6000/rs6000.h (PREDICATE_CODES): Remove rldic_operand.
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* config/rs6000/rs6000.md <ashldi3_internal 64 bit patterns>:
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Replace match_operand rldic_operand predicate with
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const_int_operand. Replace includes_lshift64_p condition with
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includes_rldic_lshift_p.
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<ashldi3_internal 64 bit rldicr patterns>: New.
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2001-08-27 Andreas Jaeger <aj@suse.de>
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* emit-rtl.c: Use VA_OPEN/VA_CLOSE/VA_FIXEDARG throughout.
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@ -60,7 +60,6 @@ extern int non_logical_cint_operand PARAMS ((rtx, enum machine_mode));
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extern int logical_operand PARAMS ((rtx, enum machine_mode));
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extern int mask_operand PARAMS ((rtx, enum machine_mode));
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extern int mask64_operand PARAMS ((rtx, enum machine_mode));
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extern int rldic_operand PARAMS ((rtx, enum machine_mode));
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extern int and64_operand PARAMS ((rtx, enum machine_mode));
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extern int and_operand PARAMS ((rtx, enum machine_mode));
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extern int count_register_operand PARAMS ((rtx, enum machine_mode));
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@ -86,7 +85,8 @@ extern int boolean_or_operator PARAMS ((rtx, enum machine_mode));
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extern int min_max_operator PARAMS ((rtx, enum machine_mode));
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extern int includes_lshift_p PARAMS ((rtx, rtx));
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extern int includes_rshift_p PARAMS ((rtx, rtx));
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extern int includes_lshift64_p PARAMS ((rtx, rtx));
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extern int includes_rldic_lshift_p PARAMS ((rtx, rtx));
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extern int includes_rldicr_lshift_p PARAMS ((rtx, rtx));
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extern int registers_ok_for_quad_peep PARAMS ((rtx, rtx));
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extern int addrs_ok_for_quad_peep PARAMS ((rtx, rtx));
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extern enum reg_class secondary_reload_class PARAMS ((enum reg_class,
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@ -1158,26 +1158,36 @@ mask_operand (op, mode)
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register rtx op;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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HOST_WIDE_INT c;
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int i;
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int last_bit_value;
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int transitions = 0;
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unsigned HOST_WIDE_INT c, lsb;
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if (GET_CODE (op) != CONST_INT)
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return 0;
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c = INTVAL (op);
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if (c == 0 || c == ~0)
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/* We don't change the number of transitions by inverting,
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so make sure we start with the LS bit zero. */
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if (c & 1)
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c = ~c;
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/* Reject all zeros or all ones. */
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if (c == 0)
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return 0;
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last_bit_value = c & 1;
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/* Find the first transition. */
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lsb = c & -c;
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for (i = 1; i < 32; i++)
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if (((c >>= 1) & 1) != last_bit_value)
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last_bit_value ^= 1, transitions++;
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/* Invert to look for a second transition. */
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c = ~c;
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return transitions <= 2;
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/* Erase first transition. */
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c &= -lsb;
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/* Find the second transition (if any). */
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lsb = c & -c;
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/* Match if all the bits above are 1's (or c is zero). */
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return c == -lsb;
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}
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/* Return 1 if the operand is a constant that is a PowerPC64 mask.
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@ -1192,133 +1202,49 @@ mask64_operand (op, mode)
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{
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if (GET_CODE (op) == CONST_INT)
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{
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HOST_WIDE_INT c = INTVAL (op);
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int i;
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int last_bit_value;
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int transitions = 0;
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unsigned HOST_WIDE_INT c, lsb;
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if (c == 0 || c == ~0)
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/* We don't change the number of transitions by inverting,
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so make sure we start with the LS bit zero. */
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c = INTVAL (op);
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if (c & 1)
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c = ~c;
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/* Reject all zeros or all ones. */
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if (c == 0)
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return 0;
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last_bit_value = c & 1;
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for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
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if (((c >>= 1) & 1) != last_bit_value)
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last_bit_value ^= 1, transitions++;
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return transitions <= 1;
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/* Find the transition, and check that all bits above are 1's. */
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lsb = c & -c;
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return c == -lsb;
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}
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else if (GET_CODE (op) == CONST_DOUBLE
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&& (mode == VOIDmode || mode == DImode))
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{
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HOST_WIDE_INT low = CONST_DOUBLE_LOW (op);
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#if HOST_BITS_PER_WIDE_INT == 32
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HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op);
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#endif
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int i;
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int last_bit_value;
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int transitions = 0;
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unsigned HOST_WIDE_INT low, high, lsb;
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if ((low == 0
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#if HOST_BITS_PER_WIDE_INT == 32
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&& high == 0
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#endif
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)
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|| (low == ~0
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#if HOST_BITS_PER_WIDE_INT == 32
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&& high == ~0
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#endif
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))
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return 0;
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if (HOST_BITS_PER_WIDE_INT < 64)
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high = CONST_DOUBLE_HIGH (op);
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last_bit_value = low & 1;
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low = CONST_DOUBLE_LOW (op);
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if (low & 1)
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{
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if (HOST_BITS_PER_WIDE_INT < 64)
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high = ~high;
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low = ~low;
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}
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for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
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if (((low >>= 1) & 1) != last_bit_value)
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last_bit_value ^= 1, transitions++;
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if (low == 0)
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{
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if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)
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return 0;
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#if HOST_BITS_PER_WIDE_INT == 32
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if ((high & 1) != last_bit_value)
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last_bit_value ^= 1, transitions++;
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lsb = high & -high;
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return high == -lsb;
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}
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for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
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if (((high >>= 1) & 1) != last_bit_value)
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last_bit_value ^= 1, transitions++;
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#endif
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return transitions <= 1;
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}
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else
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return 0;
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}
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/* Return 1 if the operand is a constant that is a PowerPC64 mask.
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It is if there are no more than two 1->0 or 0->1 transitions.
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Reject all ones and all zeros, since these should have been optimized
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away and confuse the making of MB and ME. */
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int
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rldic_operand (op, mode)
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register rtx op;
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enum machine_mode mode;
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{
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if (GET_CODE (op) == CONST_INT)
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{
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HOST_WIDE_INT c = INTVAL (op);
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int i;
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int last_bit_value;
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int transitions = 0;
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if (c == 0 || c == ~0)
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return 0;
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last_bit_value = c & 1;
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for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
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if (((c >>= 1) & 1) != last_bit_value)
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last_bit_value ^= 1, transitions++;
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return transitions <= 2;
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}
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else if (GET_CODE (op) == CONST_DOUBLE
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&& (mode == VOIDmode || mode == DImode))
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{
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HOST_WIDE_INT low = CONST_DOUBLE_LOW (op);
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#if HOST_BITS_PER_WIDE_INT == 32
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HOST_WIDE_INT high = CONST_DOUBLE_HIGH (op);
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#endif
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int i;
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int last_bit_value;
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int transitions = 0;
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if ((low == 0
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#if HOST_BITS_PER_WIDE_INT == 32
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&& high == 0
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#endif
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)
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|| (low == ~0
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#if HOST_BITS_PER_WIDE_INT == 32
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&& high == ~0
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#endif
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))
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return 0;
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last_bit_value = low & 1;
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for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
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if (((low >>= 1) & 1) != last_bit_value)
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last_bit_value ^= 1, transitions++;
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#if HOST_BITS_PER_WIDE_INT == 32
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if ((high & 1) != last_bit_value)
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last_bit_value ^= 1, transitions++;
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for (i = 1; i < HOST_BITS_PER_WIDE_INT; i++)
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if (((high >>= 1) & 1) != last_bit_value)
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last_bit_value ^= 1, transitions++;
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#endif
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return transitions <= 2;
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lsb = low & -low;
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return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
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}
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else
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return 0;
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@ -3705,36 +3631,174 @@ includes_rshift_p (shiftop, andop)
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return (INTVAL (andop) & ~shift_mask) == 0;
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}
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/* Return 1 if ANDOP is a mask that has no bits on that are not in the
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mask required to convert the result of a rotate insn into a shift
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left insn of SHIFTOP bits. */
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/* Return 1 if ANDOP is a mask suitable for use with an rldic insn
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to perform a left shift. It must have exactly SHIFTOP least
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signifigant 0's, then one or more 1's, then zero or more 0's. */
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int
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includes_lshift64_p (shiftop, andop)
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includes_rldic_lshift_p (shiftop, andop)
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register rtx shiftop;
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register rtx andop;
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{
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#if HOST_BITS_PER_WIDE_INT == 64
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unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
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shift_mask <<= INTVAL (shiftop);
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return (INTVAL (andop) & ~shift_mask) == 0;
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#else
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unsigned HOST_WIDE_INT shift_mask_low = ~(unsigned HOST_WIDE_INT) 0;
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unsigned HOST_WIDE_INT shift_mask_high = ~(unsigned HOST_WIDE_INT) 0;
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shift_mask_low <<= INTVAL (shiftop);
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if (INTVAL (shiftop) > 32)
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shift_mask_high <<= (INTVAL (shiftop) - 32);
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if (GET_CODE (andop) == CONST_INT)
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return (INTVAL (andop) & ~shift_mask_low) == 0;
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{
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unsigned HOST_WIDE_INT c, lsb, shift_mask;
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c = INTVAL (andop);
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if (c == 0 || c == ~(unsigned HOST_WIDE_INT) 0)
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return 0;
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shift_mask = ~(unsigned HOST_WIDE_INT) 0;
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shift_mask <<= INTVAL (shiftop);
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/* Find the least signifigant one bit. */
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lsb = c & -c;
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/* It must coincide with the LSB of the shift mask. */
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if (-lsb != shift_mask)
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return 0;
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/* Invert to look for the next transition (if any). */
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c = ~c;
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/* Remove the low group of ones (originally low group of zeros). */
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c &= -lsb;
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/* Again find the lsb, and check we have all 1's above. */
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lsb = c & -c;
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return c == -lsb;
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}
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else if (GET_CODE (andop) == CONST_DOUBLE
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&& (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
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{
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unsigned HOST_WIDE_INT low, high, lsb;
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unsigned HOST_WIDE_INT shift_mask_low, shift_mask_high;
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low = CONST_DOUBLE_LOW (andop);
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if (HOST_BITS_PER_WIDE_INT < 64)
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high = CONST_DOUBLE_HIGH (andop);
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if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
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|| (low == ~(unsigned HOST_WIDE_INT) 0
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&& (HOST_BITS_PER_WIDE_INT >= 64
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|| high == ~(unsigned HOST_WIDE_INT) 0)))
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return 0;
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if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
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{
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shift_mask_high = ~(unsigned HOST_WIDE_INT) 0;
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if (INTVAL (shiftop) > 32)
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shift_mask_high <<= INTVAL (shiftop) - 32;
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lsb = high & -high;
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if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
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return 0;
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high = ~high;
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high &= -lsb;
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lsb = high & -high;
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return high == -lsb;
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}
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shift_mask_low = ~(unsigned HOST_WIDE_INT) 0;
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shift_mask_low <<= INTVAL (shiftop);
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lsb = low & -low;
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if (-lsb != shift_mask_low)
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return 0;
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if (HOST_BITS_PER_WIDE_INT < 64)
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high = ~high;
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low = ~low;
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low &= -lsb;
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if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
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{
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lsb = high & -high;
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return high == -lsb;
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}
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lsb = low & -low;
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return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
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}
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else
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return ((CONST_DOUBLE_HIGH (andop) & ~shift_mask_high) == 0
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&& (CONST_DOUBLE_LOW (andop) & ~shift_mask_low) == 0);
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#endif
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return 0;
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}
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/* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
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to perform a left shift. It must have SHIFTOP or more least
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signifigant 0's, with the remainder of the word 1's. */
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int
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includes_rldicr_lshift_p (shiftop, andop)
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register rtx shiftop;
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register rtx andop;
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{
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if (GET_CODE (andop) == CONST_INT)
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{
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unsigned HOST_WIDE_INT c, lsb;
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unsigned HOST_WIDE_INT shift_mask;
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shift_mask = ~(unsigned HOST_WIDE_INT) 0;
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shift_mask <<= INTVAL (shiftop);
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c = INTVAL (andop);
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/* Find the least signifigant one bit. */
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lsb = c & -c;
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/* It must be covered by the shift mask.
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This test also rejects c == 0. */
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if ((lsb & shift_mask) == 0)
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return 0;
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/* Check we have all 1's above the transition, and reject all 1's. */
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return c == -lsb && lsb != 1;
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}
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else if (GET_CODE (andop) == CONST_DOUBLE
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&& (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
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{
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unsigned HOST_WIDE_INT low, lsb, shift_mask_low;
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low = CONST_DOUBLE_LOW (andop);
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if (HOST_BITS_PER_WIDE_INT < 64)
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{
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unsigned HOST_WIDE_INT high, shift_mask_high;
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high = CONST_DOUBLE_HIGH (andop);
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if (low == 0)
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{
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shift_mask_high = ~(unsigned HOST_WIDE_INT) 0;
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if (INTVAL (shiftop) > 32)
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shift_mask_high <<= INTVAL (shiftop) - 32;
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lsb = high & -high;
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if ((lsb & shift_mask_high) == 0)
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return 0;
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return high == -lsb;
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}
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if (high != ~0)
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return 0;
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}
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shift_mask_low = ~(unsigned HOST_WIDE_INT) 0;
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shift_mask_low <<= INTVAL (shiftop);
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lsb = low & -low;
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if ((lsb & shift_mask_low) == 0)
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return 0;
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||||
|
||||
return low == -lsb && lsb != 1;
|
||||
}
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
|
||||
|
|
@ -4537,9 +4601,6 @@ print_operand (file, x, code)
|
|||
|
||||
case 'W':
|
||||
/* MB value for a PowerPC64 rldic operand. */
|
||||
if (! rldic_operand (x, VOIDmode))
|
||||
output_operand_lossage ("invalid %%W value");
|
||||
|
||||
val = (GET_CODE (x) == CONST_INT
|
||||
? INTVAL (x) : CONST_DOUBLE_HIGH (x));
|
||||
|
||||
|
|
|
|||
|
|
@ -2585,7 +2585,6 @@ do { \
|
|||
{"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
|
||||
{"mask_operand", {CONST_INT}}, \
|
||||
{"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
|
||||
{"rldic_operand", {CONST_INT, CONST_DOUBLE}}, \
|
||||
{"count_register_operand", {REG}}, \
|
||||
{"xer_operand", {REG}}, \
|
||||
{"call_operand", {SYMBOL_REF, REG}}, \
|
||||
|
|
|
|||
|
|
@ -6559,8 +6559,8 @@
|
|||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
|
||||
(match_operand:SI 2 "const_int_operand" "i"))
|
||||
(match_operand:DI 3 "rldic_operand" "n")))]
|
||||
"TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3])"
|
||||
(match_operand:DI 3 "const_int_operand" "n")))]
|
||||
"TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
|
||||
"rldic %0,%1,%H2,%W3")
|
||||
|
||||
(define_insn "ashldi3_internal5"
|
||||
|
|
@ -6568,10 +6568,10 @@
|
|||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "const_int_operand" "i,i"))
|
||||
(match_operand:DI 3 "rldic_operand" "n,n"))
|
||||
(match_operand:DI 3 "const_int_operand" "n,n"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 4 "=r,r"))]
|
||||
"TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3])"
|
||||
"TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
|
||||
"@
|
||||
rldic. %4,%1,%H2,%W3
|
||||
#"
|
||||
|
|
@ -6583,10 +6583,11 @@
|
|||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "const_int_operand" ""))
|
||||
(match_operand:DI 3 "rldic_operand" ""))
|
||||
(match_operand:DI 3 "const_int_operand" ""))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 4 ""))]
|
||||
"TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3]) && reload_completed"
|
||||
"TARGET_POWERPC64 && reload_completed
|
||||
&& includes_rldic_lshift_p (operands[2], operands[3])"
|
||||
[(set (match_dup 4)
|
||||
(and:DI (ashift:DI (match_dup 1) (match_dup 2))
|
||||
(match_dup 3)))
|
||||
|
|
@ -6600,11 +6601,11 @@
|
|||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "const_int_operand" "i,i"))
|
||||
(match_operand:DI 3 "rldic_operand" "n,n"))
|
||||
(match_operand:DI 3 "const_int_operand" "n,n"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3])"
|
||||
"TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
|
||||
"@
|
||||
rldic. %0,%1,%H2,%W3
|
||||
#"
|
||||
|
|
@ -6616,11 +6617,88 @@
|
|||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "const_int_operand" ""))
|
||||
(match_operand:DI 3 "rldic_operand" ""))
|
||||
(match_operand:DI 3 "const_int_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3]) && reload_completed"
|
||||
"TARGET_POWERPC64 && reload_completed
|
||||
&& includes_rldic_lshift_p (operands[2], operands[3])"
|
||||
[(set (match_dup 0)
|
||||
(and:DI (ashift:DI (match_dup 1) (match_dup 2))
|
||||
(match_dup 3)))
|
||||
(set (match_dup 4)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn "*ashldi3_internal7"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
|
||||
(match_operand:SI 2 "const_int_operand" "i"))
|
||||
(match_operand:DI 3 "mask64_operand" "S")))]
|
||||
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
|
||||
"rldicr %0,%1,%H2,%S3")
|
||||
|
||||
(define_insn "ashldi3_internal8"
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "const_int_operand" "i,i"))
|
||||
(match_operand:DI 3 "mask64_operand" "S,S"))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 4 "=r,r"))]
|
||||
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
|
||||
"@
|
||||
rldicr. %4,%1,%H2,%S3
|
||||
#"
|
||||
[(set_attr "type" "delayed_compare")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "const_int_operand" ""))
|
||||
(match_operand:DI 3 "mask64_operand" ""))
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 4 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed
|
||||
&& includes_rldicr_lshift_p (operands[2], operands[3])"
|
||||
[(set (match_dup 4)
|
||||
(and:DI (ashift:DI (match_dup 1) (match_dup 2))
|
||||
(match_dup 3)))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 4)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn "*ashldi3_internal9"
|
||||
[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
|
||||
(match_operand:SI 2 "const_int_operand" "i,i"))
|
||||
(match_operand:DI 3 "mask64_operand" "S,S"))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
|
||||
"@
|
||||
rldicr. %0,%1,%H2,%S3
|
||||
#"
|
||||
[(set_attr "type" "delayed_compare")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
|
||||
(compare:CC
|
||||
(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:SI 2 "const_int_operand" ""))
|
||||
(match_operand:DI 3 "mask64_operand" ""))
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"TARGET_POWERPC64 && reload_completed
|
||||
&& includes_rldicr_lshift_p (operands[2], operands[3])"
|
||||
[(set (match_dup 0)
|
||||
(and:DI (ashift:DI (match_dup 1) (match_dup 2))
|
||||
(match_dup 3)))
|
||||
|
|
|
|||
Loading…
Reference in New Issue