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re PR target/8603 ([Alpha] s?addl pattern doesn't work)

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PR target/8603
	* config/alpha/alpha.md (addsi3): Remove expander.
	(addsi3): Rename from *addsi3_internal insn pattern.
	(subsi3): Remove expander.
	(subsi3): Rename from *subsi3_internal insn pattern.

From-SVN: r150654
This commit is contained in:
Uros Bizjak 2009-08-11 19:05:38 +02:00
parent b0d0a8a7c9
commit c53c2591f6
2 changed files with 21 additions and 32 deletions
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33
gcc/ChangeLog
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@ -1,11 +1,19 @@
2009-08-11 Uros Bizjak <ubizjak@gmail.com>
PR target/8603
* config/alpha/alpha.md (addsi3): Remove expander.
(addsi3): Rename from *addsi3_internal insn pattern.
(subsi3): Remove expander.
(subsi3): Rename from *subsi3_internal insn pattern.
2009-08-11 Douglas B Rupp <rupp@gnat.com>
* config/alpha/alpha.c (alpha_init_builtins): Nullify FWRITE and
FWRITE_UNLOCKED.
2009-08-11 Vasiliy Fofanov <fofanov@adacore.com>
Eric Botcazou <botcazou@adacore.com>
Douglas B Rupp <rupp@gnat.com>
Eric Botcazou <botcazou@adacore.com>
Douglas B Rupp <rupp@gnat.com>
* config/alpha/alpha.c (alpha_return_in_memory): On VMS, ensure
that records that fit in 64 bits are returned by immediate value,
@ -22,10 +30,9 @@
not valid in the outer mode.
2009-08-11 Richard Guenther <rguenther@suse.de>
PR bootstrap/40788
* builtins.c (gimplify_va_arg_expr): Do not call
SET_EXPR_LOCATION.
PR bootstrap/40788
* builtins.c (gimplify_va_arg_expr): Do not call SET_EXPR_LOCATION.
2009-08-10 Douglas B Rupp <rupp@gnat.com>
@ -33,7 +40,7 @@
(OVERRIDE_OPTIONS): Incorporate removed OPTIMIZATION_OPTIONS.
2009-08-10 Olivier Hainque <hainqueu@adacore.com>
Douglas B Rupp <rupp@gnat.com>
Douglas B Rupp <rupp@gnat.com>
* config/alpha/alpha.c (alpha_sa_size): Force procedure type to
PT_STACK when frame_pointer_needed on OpenVMS.
@ -52,7 +59,7 @@
Call alpha_vms_can_eliminate and alpha_vms_initial_elimination_offset.
2009-08-10 Eric Botcazou <botcazou@adacore.com>
Douglas B Rupp <rupp@gnat.com>
Douglas B Rupp <rupp@gnat.com>
* config/alpha/alpha.c (common_object_handler): New function.
(vms_attribute_table): Declare a single attribute "common_object".
@ -116,7 +123,7 @@
doc/invoke.texi (mmalloc64): Document switch.
2009-08-09 Olivier Hainque <hainque@adacore.com>
Douglas B Rupp <rupp@gnat.com>
Douglas B Rupp <rupp@gnat.com>
* config/alpha/alpha.c (struct machine_function): New flag for VMS,
uses_condition_handler.
@ -145,7 +152,7 @@
* config/alpha/vms.h (MD_UNWIND_SUPPORT):
2009-08-09 Eric Botcazou <botcazou@adacore.com>
Douglas B Rupp <rupp@gnat.com>
Douglas B Rupp <rupp@gnat.com>
* config/alpha/alpha.c (alpha_links): Add 'target' field.
(alpha_need_linkage): Handle aliases. Return function symbol.
@ -203,8 +210,7 @@
2009-08-09 Richard Guenther <rguenther@suse.de>
PR tree-optimization/41016
* tree-ssa-ifcombine.c (get_name_for_bit_test): Fix tuplification
bug.
* tree-ssa-ifcombine.c (get_name_for_bit_test): Fix tuplification bug.
(operand_precision): Remove.
(integral_operand_p): Likewise.
(recognize_single_bit_test): Adjust.
@ -252,8 +258,7 @@
(force_expr_to_var_cost): Cast target_spill_cost to int.
(get_address_cost): New arguments STMT_AFTER_INC and MAY_AUTOINC.
All callers changed. Check for availability of autoinc addressing
modes, both in general for a given mode, and in the specific use
case.
modes, both in general for a given mode, and in the specific use case.
(get_computation_cost_at): New argument CAN_AUTOINC. All callers
changed.
(get_computation_cost): Likewise.

20
gcc/config/alpha/alpha.md
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@ -256,16 +256,7 @@
(sign_extend:DI (match_dup 1)))]
"")
;; Don't say we have addsi3 if optimizing. This generates better code. We
;; have the anonymous addsi3 pattern below in case combine wants to make it.
(define_expand "addsi3"
[(set (match_operand:SI 0 "register_operand" "")
(plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "add_operand" "")))]
"! optimize"
"")
(define_insn "*addsi_internal"
(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
(match_operand:SI 2 "add_operand" "rI,O,K,L")))]
@ -619,14 +610,7 @@
""
"subqv $31,%1,%0")
(define_expand "subsi3"
[(set (match_operand:SI 0 "register_operand" "")
(minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
(match_operand:SI 2 "reg_or_8bit_operand" "")))]
"! optimize"
"")
(define_insn "*subsi_internal"
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "reg_or_8bit_operand" "rI")))]