pdp11.md: Correct length attribute for float literal case.
* config/pdp11/pdp11.md: Correct length attribute for float literal case. From-SVN: r168295
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@ -1,3 +1,8 @@
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2010-12-28 Paul Koning <ni1d@arrl.net>
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* config/pdp11/pdp11.md: Correct length attribute for float
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literal case.
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2010-12-28 Jie Zhang <jie@codesourcery.com>
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* builtins.c (SLOW_UNALIGNED_ACCESS): Remove.
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@ -98,9 +98,9 @@
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(define_asm_attributes
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[(set_attr "type" "unknown")
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; length for asm is the max length per statement. That would be
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; 5 words, for a floating point instruction with a literal constant
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; argument.
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(set_attr "length" "10")])
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; 3 words, for a two-operand instruction with extra word addressing
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; modes for both operands.
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(set_attr "length" "6")])
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;; define function units
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@ -114,8 +114,8 @@
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;; compare
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(define_insn "*cmpdf"
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[(set (cc0)
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(compare (match_operand:DF 0 "general_operand" "fR,fR,Q,Q,F")
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(match_operand:DF 1 "register_or_const0_operand" "G,a,G,a,a")))]
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(compare (match_operand:DF 0 "general_operand" "fR,fR,Q,QF")
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(match_operand:DF 1 "register_or_const0_operand" "G,a,G,a")))]
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"TARGET_FPU"
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"*
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{
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@ -125,7 +125,7 @@
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else
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return \"{cmpd|cmpf} %0, %1\;cfcc\";
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}"
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[(set_attr "length" "4,4,6,6,12")])
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[(set_attr "length" "4,4,6,6")])
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(define_insn "*cmp<mode>"
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[(set (cc0)
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@ -291,7 +291,7 @@
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(define_insn "movdf"
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[(set (match_operand:DF 0 "float_nonimm_operand" "=a,fR,a,Q,g")
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(match_operand:DF 1 "float_operand" "fFR,a,Q,a,g"))]
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(match_operand:DF 1 "float_operand" "fR,a,FQ,a,g"))]
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"TARGET_FPU"
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"* if (which_alternative ==0 || which_alternative == 2)
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return \"ldd %1, %0\";
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@ -299,12 +299,12 @@
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return \"std %1, %0\";
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else
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return output_move_multiple (operands); "
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;; just a guess..
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[(set_attr "length" "2,2,10,10,32")])
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;; last one is worst-case
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[(set_attr "length" "2,2,4,4,24")])
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(define_insn "movsf"
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[(set (match_operand:SF 0 "float_nonimm_operand" "=a,fR,a,Q,g")
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(match_operand:SF 1 "float_operand" "fFR,a,Q,a,g"))]
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(match_operand:SF 1 "float_operand" "fR,a,FQ,a,g"))]
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"TARGET_FPU"
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"* if (which_alternative ==0 || which_alternative == 2)
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return \"{ldcfd|movof} %1, %0\";
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@ -312,8 +312,8 @@
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return \"{stcdf|movfo} %1, %0\";
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else
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return output_move_multiple (operands); "
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;; just a guess..
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[(set_attr "length" "2,2,10,10,16")])
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;; last one is worst-case
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[(set_attr "length" "2,2,4,4,12")])
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;; maybe fiddle a bit with move_ratio, then
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;; let constraints only accept a register ...
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@ -607,12 +607,12 @@
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;;- add instructions
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(define_insn "adddf3"
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[(set (match_operand:DF 0 "register_operand" "=a,a,a")
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(plus:DF (match_operand:DF 1 "register_operand" "%0,0,0")
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(match_operand:DF 2 "general_operand" "fR,Q,F")))]
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[(set (match_operand:DF 0 "register_operand" "=a,a")
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(plus:DF (match_operand:DF 1 "register_operand" "%0,0")
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(match_operand:DF 2 "general_operand" "fR,QF")))]
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"TARGET_FPU"
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"{addd|addf} %2, %0"
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[(set_attr "length" "2,4,10")])
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[(set_attr "length" "2,4")])
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(define_insn "adddi3"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=&r,r,o,o")
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@ -1261,12 +1261,12 @@
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;;- multiply
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(define_insn "muldf3"
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[(set (match_operand:DF 0 "register_operand" "=a,a,a")
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(mult:DF (match_operand:DF 1 "register_operand" "%0,0,0")
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(match_operand:DF 2 "float_operand" "fR,Q,F")))]
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[(set (match_operand:DF 0 "register_operand" "=a,a")
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(mult:DF (match_operand:DF 1 "register_operand" "%0,0")
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(match_operand:DF 2 "float_operand" "fR,QF")))]
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"TARGET_FPU"
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"{muld|mulf} %2, %0"
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[(set_attr "length" "2,4,10")])
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[(set_attr "length" "2,4")])
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;; 16 bit result multiply:
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;; currently we multiply only into odd registers, so we don't use two
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@ -1313,12 +1313,12 @@
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;;- divide
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(define_insn "divdf3"
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[(set (match_operand:DF 0 "register_operand" "=a,a,a")
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(div:DF (match_operand:DF 1 "register_operand" "0,0,0")
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(match_operand:DF 2 "general_operand" "fR,Q,F")))]
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[(set (match_operand:DF 0 "register_operand" "=a,a")
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(div:DF (match_operand:DF 1 "register_operand" "0,0")
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(match_operand:DF 2 "general_operand" "fR,QF")))]
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"TARGET_FPU"
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"{divd|divf} %2, %0"
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[(set_attr "length" "2,4,10")])
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[(set_attr "length" "2,4")])
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(define_expand "divhi3"
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