[RS6000] Rename NON_SPECIAL_REGS to GEN_OR_FLOAT_REGS

* config/rs6000/rs6000.h: Rename NON_SPECIAL_REGS to GEN_OR_FLOAT_REGS
	throughout file.
	* config/rs6000/darwin.h: Likewise.
	* config/rs6000/rs6000.c: Likewise.

From-SVN: r269960
This commit is contained in:
Alan Modra 2019-03-27 11:45:50 +10:30 committed by Alan Modra
parent 914be15cf3
commit c686fcbc77
4 changed files with 14 additions and 7 deletions

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@ -1,3 +1,10 @@
2019-03-27 Alan Modra <amodra@gmail.com>
* config/rs6000/rs6000.h: Rename NON_SPECIAL_REGS to GEN_OR_FLOAT_REGS
throughout file.
* config/rs6000/darwin.h: Likewise.
* config/rs6000/rs6000.c: Likewise.
2019-03-27 Alan Modra <amodra@gmail.com>
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Always

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@ -346,7 +346,7 @@ extern int darwin_emit_branch_islands;
&& reg_class_subset_p (BASE_REGS, (CLASS))) \
? BASE_REGS \
: (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
&& (CLASS) == NON_SPECIAL_REGS) \
&& (CLASS) == GEN_OR_FLOAT_REGS) \
? GENERAL_REGS \
: (CLASS))

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@ -20236,7 +20236,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
return NO_REGS;
}
if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
if (GET_MODE_CLASS (mode) == MODE_INT && rclass == GEN_OR_FLOAT_REGS)
return GENERAL_REGS;
return rclass;
@ -20384,7 +20384,7 @@ rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
/* Constants, memory, and FP registers can go into FP registers. */
if ((regno == -1 || FP_REGNO_P (regno))
&& (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
&& (rclass == FLOAT_REGS || rclass == GEN_OR_FLOAT_REGS))
return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
/* Memory, and AltiVec registers can go into AltiVec registers. */
@ -36154,7 +36154,7 @@ rs6000_libcall_value (machine_mode mode)
}
/* Compute register pressure classes. We implement the target hook to avoid
IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
IRA picking something like GEN_OR_FLOAT_REGS as a pressure class, which can
lead to incorrect estimates of number of available registers and therefor
increased register pressure/spill. */
static int

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@ -1138,7 +1138,7 @@ enum reg_class
VRSAVE_REGS,
VSCR_REGS,
SPR_REGS,
NON_SPECIAL_REGS,
GEN_OR_FLOAT_REGS,
LINK_REGS,
CTR_REGS,
LINK_OR_CTR_REGS,
@ -1167,7 +1167,7 @@ enum reg_class
"VRSAVE_REGS", \
"VSCR_REGS", \
"SPR_REGS", \
"NON_SPECIAL_REGS", \
"GEN_OR_FLOAT_REGS", \
"LINK_REGS", \
"CTR_REGS", \
"LINK_OR_CTR_REGS", \
@ -1204,7 +1204,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \
/* SPR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
/* NON_SPECIAL_REGS. */ \
/* GEN_OR_FLOAT_REGS. */ \
{ 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \
/* LINK_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \