(smulsi3_highpart, umulsi3_highpart, mulsidi3, umulsidi3):
Make these conditional on TARGET_MULTM. (multm matcher): Delete. (multmu matcher): Delete. (mulsidi3 DEFINE_SPLIT): Generate RTL for smulsi3_highpart instead of for deleted pattern. Fix typo in preparation code. (umulsidi3 DEFINE_SPLIT): Analogous change. From-SVN: r8920
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f9151c433c
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c694e02fd1
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@ -1120,32 +1120,12 @@
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""
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"multiply %0,%1,%2")
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(subreg:SI
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(mult:DI
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(sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
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(sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))
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(clobber (match_scratch:SI 3 "=&q"))]
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""
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"multm %0,%1,%2")
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(define_insn ""
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(subreg:SI
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(mult:DI
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(zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
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(zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))) 0))
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(clobber (match_scratch:SI 3 "=&q"))]
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""
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"multmu %0,%1,%2")
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(define_insn "mulsidi3"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
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(sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
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(clobber (match_scratch:SI 3 "=&q"))]
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""
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"TARGET_MULTM"
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"multiply %L0,%1,%2\;multm %0,%1,%2"
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[(set_attr "type" "multi")])
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@ -1159,20 +1139,22 @@
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(mult:SI (match_dup 1) (match_dup 2)))
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(clobber (reg:SI 180))])
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(parallel [(set (match_dup 4)
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(subreg:SI (mult:DI
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(sign_extend:DI (match_dup 1))
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(sign_extend:DI (match_dup 2))) 0))
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(truncate:SI
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(lshiftrt:DI
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(mult:DI (sign_extend:DI (match_dup 1))
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(sign_extend:DI (match_dup 2)))
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(const_int 32))))
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(clobber (reg:SI 180))])]
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"
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{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
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operands[4] = operand_subword (operands[1], 0, 1, DImode); } ")
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operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
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(define_insn "umulsidi3"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
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(zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
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(clobber (match_scratch:SI 3 "=&q"))]
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""
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"TARGET_MULTM"
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"multiplu %L0,%1,%2\;multmu %0,%1,%2"
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[(set_attr "type" "multi")])
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@ -1186,12 +1168,15 @@
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(mult:SI (match_dup 1) (match_dup 2)))
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(clobber (reg:SI 180))])
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(parallel [(set (match_dup 4)
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(subreg:SI (mult:DI (zero_extend:DI (match_dup 1))
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(zero_extend:DI (match_dup 2))) 0))
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(truncate:SI
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(lshiftrt:DI
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(mult:DI (zero_extend:DI (match_dup 1))
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(zero_extend:DI (match_dup 2)))
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(const_int 32))))
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(clobber (reg:SI 180))])]
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"
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{ operands[3] = operand_subword (operands[0], 1, 1, DImode);
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operands[4] = operand_subword (operands[1], 0, 1, DImode); } ")
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operands[4] = operand_subword (operands[0], 0, 1, DImode); } ")
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(define_insn "smulsi3_highpart"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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@ -1201,7 +1186,7 @@
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(sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=&q"))]
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""
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"TARGET_MULTM"
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"multm %0,%1,%2")
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(define_insn "umulsi3_highpart"
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@ -1212,7 +1197,7 @@
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(zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=&q"))]
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""
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"TARGET_MULTM"
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"multmu %0,%1,%2")
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;; NAND
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