(BYTE_LOAD_EXTEND, LOAD_EXTEND): New macros.
(subst, simplify_and_const_int, nonzero_bits, num_sign_bit_copies): Use them. (subst, case SET): Make a SIGN_EXTEND instead of paradoxical SUBREG if BYTE_LOADS_SIGN_EXTEND; previously only made ZERO_EXTEND. From-SVN: r3160
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@ -92,6 +92,20 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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Use gen_lowpart_for_combine instead. See comments there. */
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#define gen_lowpart dont_use_gen_lowpart_you_dummy
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/* If byte loads either zero- or sign- extend, define BYTE_LOADS_EXTEND
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for cases when we don't care which is true. Define LOAD_EXTEND to
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be ZERO_EXTEND or SIGN_EXTEND, depending on which was defined. */
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#ifdef BYTE_LOADS_ZERO_EXTEND
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#define BYTE_LOADS_EXTEND
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#define LOAD_EXTEND ZERO_EXTEND
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#endif
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#ifdef BYTE_LOAD_SIGN_EXTEND
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#define BYTE_LOADS_EXTEND
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#define LOAD_EXTEND SIGN_EXTEND
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#endif
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/* Number of attempts to combine instructions in this function. */
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static int combine_attempts;
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@ -3822,8 +3836,8 @@ subst (x, from, to, in_dest, unique_copy)
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We can always do this if M1 is narrower than M2 because that
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means that we only care about the low bits of the result.
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However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
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and BYTES_LOADS_SIGN_EXTEND not defined), we cannot perform a
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However, on most machines (those with neither BYTE_LOADS_ZERO_EXTEND
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nor BYTES_LOADS_SIGN_EXTEND defined), we cannot perform a
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narrower operation that requested since the high-order bits will
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be undefined. On machine where BYTE_LOADS_*_EXTEND is defined,
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however, this transformation is safe as long as M1 and M2 have
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@ -3836,7 +3850,7 @@ subst (x, from, to, in_dest, unique_copy)
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/ UNITS_PER_WORD)
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== ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
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+ (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
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#if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined (BYTE_LOADS_SIGN_EXTEND)
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#ifndef BYTE_LOADS_EXTEND
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&& (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
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< GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
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#endif
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@ -3850,18 +3864,19 @@ subst (x, from, to, in_dest, unique_copy)
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SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
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}
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#ifdef BYTE_LOADS_ZERO_EXTEND
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#ifdef BYTE_LOADS_EXTEND
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/* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
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M wider than N, this would require a paradoxical subreg.
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Replace the subreg with a zero_extend to avoid the reload that
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would otherwise be required. */
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if (GET_CODE (SET_SRC (x)) == SUBREG
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&& subreg_lowpart_p (SET_SRC (x))
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&& SUBREG_WORD (SET_SRC (x)) == 0
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&& (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
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> GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
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&& GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
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SUBST (SET_SRC (x), gen_rtx_combine (ZERO_EXTEND,
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SUBST (SET_SRC (x), gen_rtx_combine (LOAD_EXTEND,
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GET_MODE (SET_SRC (x)),
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XEXP (SET_SRC (x), 0)));
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#endif
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@ -5675,7 +5690,7 @@ simplify_and_const_int (x, mode, varop, constop)
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constant masks to zero all the bits the mode doesn't have. */
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&& ((GET_MODE_SIZE (GET_MODE (varop))
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< GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
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#if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
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#ifdef BYTE_LOADS_EXTEND
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|| (0 == (constop
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& GET_MODE_MASK (GET_MODE (varop))
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& ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
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@ -6144,7 +6159,7 @@ nonzero_bits (x, mode)
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<= HOST_BITS_PER_WIDE_INT))
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{
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nonzero &= nonzero_bits (SUBREG_REG (x), mode);
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#if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined(BYTE_LOADS_SIGN_EXTEND)
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#ifndef BYTE_LOADS_EXTEND
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/* On many CISC machines, accessing an object in a wider mode
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causes the high-order bits to become undefined. So they are
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not known to be zero. */
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@ -6290,7 +6305,7 @@ num_sign_bit_copies (x, mode)
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- bitwidth)));
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}
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#if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
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#ifdef BYTE_LOADS_EXTEND
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/* For paradoxical SUBREGs, just look inside since, on machines with
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one of these defined, we assume that operations are actually
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performed on the full register. Note that we are passing MODE
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