Minor BRIG/HSAIL frontend updates and bug fixes:
* brig-builtins.def: Added a builtin for class_f64. * builtin-types.def: Added a builtin type needed by class_f64. * brigfrontend/brig-code-entry-handler.cc (brig_code_entry_handler::build_address_operand): Fix a bug with reg+offset addressing on 32b segments. In large mode, the offset is treated as 32bits unless it's global, readonly or kernarg address space. * rt/workitems.c: Removed a leftover comment. * rt/arithmetic.c (__hsail_class_f32, __hsail_class_f64): Fix the check for signaling/non-signalling NaN. Add class_f64 default implementation. From-SVN: r247576
This commit is contained in:
parent
1738af6048
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c6e334cdb1
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@ -1,3 +1,8 @@
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2017-05-04 Pekka Jääskeläinen <pekka.jaaskelainen@parmance.com>
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* brig-builtins.def: Added a builtin for class_f64.
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* builtin-types.def: Added a builtin type needed by class_f64.
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2017-05-03 Jason Merrill <jason@redhat.com>
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* timevar.def: Add TV_CONSTEXPR.
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@ -71,6 +76,7 @@
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* ipa-inline.h (inline_summary): Add ctor.
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(create_ggc): Do not use ggc_cleared_alloc.
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>>>>>>> .r247575
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2017-05-03 Jeff Downs <heydowns@somuchpressure.net>
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Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
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@ -222,6 +222,10 @@ DEF_HSAIL_BUILTIN (BUILT_IN_HSAIL_CLASS_F32, BRIG_OPCODE_CLASS,
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BRIG_TYPE_F32, "__hsail_class_f32", BT_FN_UINT_FLOAT_UINT,
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ATTR_PURE_NOTHROW_LEAF_LIST)
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DEF_HSAIL_BUILTIN (BUILT_IN_HSAIL_CLASS_F64, BRIG_OPCODE_CLASS,
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BRIG_TYPE_F64, "__hsail_class_f64", BT_FN_UINT_DOUBLE_UINT,
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ATTR_PURE_NOTHROW_LEAF_LIST)
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DEF_HSAIL_BUILTIN (BUILT_IN_HSAIL_CLASS_F32_F16, BRIG_OPCODE_CLASS,
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BRIG_TYPE_F16, "__hsail_class_f32_f16", BT_FN_UINT_FLOAT_UINT,
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ATTR_PURE_NOTHROW_LEAF_LIST)
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@ -1,3 +1,11 @@
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2017-05-03 Pekka Jääskeläinen <visit0r@kamu>
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* brigfrontend/brig-code-entry-handler.cc
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(brig_code_entry_handler::build_address_operand): Fix a bug
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with reg+offset addressing on 32b segments. In large mode,
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the offset is treated as 32bits unless it's global, readonly or
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kernarg address space.
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2016-02-01 Pekka Jääskeläinen <pekka.jaaskelainen@parmance.com>
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* brigfrontend/brig-code-entry-handler.cc: fix address
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@ -464,7 +464,24 @@ brig_code_entry_handler::build_address_operand
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uint64_t offs = gccbrig_to_uint64_t (addr_operand.offset);
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if (offs > 0 || addr == NULL_TREE)
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{
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tree const_offset_2 = build_int_cst (size_type_node, offs);
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/* In large mode, the offset is treated as 32bits unless it's
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global, readonly or kernarg address space.
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See:
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http://www.hsafoundation.com/html_spec111/HSA_Library.htm
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#PRM/Topics/02_ProgModel/small_and_large_machine_models.htm
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#table_machine_model_data_sizes */
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int is64b_offset = segment == BRIG_SEGMENT_GLOBAL
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|| segment == BRIG_SEGMENT_READONLY
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|| segment == BRIG_SEGMENT_KERNARG;
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/* The original offset is signed and should be sign
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extended for the pointer arithmetics. */
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tree const_offset_2 = is64b_offset
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? build_int_cst (size_type_node, offs)
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: convert (long_integer_type_node,
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build_int_cst (integer_type_node, offs));
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if (addr == NULL_TREE)
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addr = const_offset_2;
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else
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@ -1265,6 +1282,10 @@ brig_code_entry_handler::build_operands (const BrigInstBase &brig_inst)
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operand_type = uint32_type_node;
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half_to_float = false;
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}
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else if (brig_inst.opcode == BRIG_OPCODE_ACTIVELANEPERMUTE && i == 4)
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{
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operand_type = uint32_type_node;
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}
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else if (half_to_float)
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/* Treat the operands as the storage type at this point. */
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operand_type = half_storage_type;
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@ -348,6 +348,8 @@ DEF_FUNCTION_TYPE_2 (BT_FN_INT_INT_INT,
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BT_INT, BT_INT, BT_INT)
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DEF_FUNCTION_TYPE_2 (BT_FN_UINT_FLOAT_UINT,
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BT_UINT, BT_FLOAT, BT_UINT)
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DEF_FUNCTION_TYPE_2 (BT_FN_UINT_DOUBLE_UINT,
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BT_UINT, BT_DOUBLE, BT_UINT)
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DEF_FUNCTION_TYPE_2 (BT_FN_FLOAT_UINT_UINT,
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BT_FLOAT, BT_UINT, BT_UINT)
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DEF_FUNCTION_TYPE_2 (BT_FN_ULONG_UINT_UINT,
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@ -1,3 +1,10 @@
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2017-05-03 Pekka Jääskeläinen <pekka.jaaskelainen@parmance.com>
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* rt/workitems.c: Removed a leftover comment.
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* rt/arithmetic.c (__hsail_class_f32, __hsail_class_f64): Fix the
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check for signaling/non-signalling NaN. Add class_f64 default
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implementation.
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2017-02-01 Jakub Jelinek <jakub@redhat.com>
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* configure.tgt: Fix i?86-*-linux* entry.
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@ -424,8 +424,8 @@ __hsail_fract_f64 (double a)
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uint32_t
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__hsail_class_f32 (float a, uint32_t flags)
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{
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return (flags & 0x0001 && isnan (a) && !(*(uint32_t *) &a & 0x40000000))
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|| (flags & 0x0002 && isnan (a) && (*(uint32_t *) &a & 0x40000000))
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return (flags & 0x0001 && isnan (a) && !(*(uint32_t *) &a & (1ul << 22)))
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|| (flags & 0x0002 && isnan (a) && (*(uint32_t *) &a & (1ul << 22)))
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|| (flags & 0x0004 && isinf (a) && a < 0.0f)
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|| (flags & 0x0008 && isnormal (a) && signbit (a))
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|| (flags & 0x0010 && a < 0.0f && a > -FLT_MIN)
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@ -436,6 +436,22 @@ __hsail_class_f32 (float a, uint32_t flags)
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|| (flags & 0x0200 && isinf (a) && a >= 0.0f);
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}
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uint32_t
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__hsail_class_f64 (double a, uint32_t flags)
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{
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return (flags & 0x0001 && isnan (a) && !(*(uint64_t *) &a & (1ul << 51)))
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|| (flags & 0x0002 && isnan (a) && (*(uint64_t *) &a & (1ul << 51)))
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|| (flags & 0x0004 && isinf (a) && a < 0.0f)
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|| (flags & 0x0008 && isnormal (a) && signbit (a))
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|| (flags & 0x0010 && a < 0.0f && a > -FLT_MIN)
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|| (flags & 0x0020 && a == 0.0f && signbit (a))
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|| (flags & 0x0040 && a == 0.0f && !signbit (a))
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|| (flags & 0x0080 && a > 0.0f && a < FLT_MIN)
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|| (flags & 0x0100 && isnormal (a) && !signbit (a))
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|| (flags & 0x0200 && isinf (a) && a >= 0.0f);
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}
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/* 'class' for a f32-converted f16 which should otherwise be treated like f32
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except for its limits. */
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@ -63,10 +63,6 @@ static clock_t start_time;
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#define FIBER_STACK_SIZE (64*1024)
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#define GROUP_SEGMENT_ALIGN 256
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/* HSA requires WGs to be executed in flat work-group id order. Enabling
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the following macro can reveal test cases that rely on the ordering,
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but is not useful for much else. */
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uint32_t __hsail_workitemabsid (uint32_t dim, PHSAWorkItem *context);
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uint32_t __hsail_workitemid (uint32_t dim, PHSAWorkItem *context);
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