arm.c (arm_rtx_costs_1, [...]): Adjust costs for comparing a constant with small negative numbers and add...
* arm.c (arm_rtx_costs_1, case TARGET_THUMB): Adjust costs for comparing a constant with small negative numbers and add costing for constants in conjunction with AND. (note_invalid_constants): Tidy previous change. (thumb_cmp_operand): Tidy. (thumb_cmpneg_operand): New function. * arm.h (CONDITIONAL_REGISTER_USAGE): Don't use HI regs if optimizing for size. (FIRST_LO_REGNUM, FIRST_HI_REGNUM, LAST_HI_REGNUM): Define. (PREDICATE_CODES): Add thumb_cmpneg_operand. * arm.md (cbranchsi4): Convert to define_expand. Handle comparison with a negative constant. (cbranchsi4_insn): Matcher for cbranchsi4. (cbranchsi4_scratch): Similar, but a scratch is available for handling negative constants. (movsi_cbranchsi4): New pattern. (tstsi3_cbranch): Renamed from andsi3_cbranch_scratch, remove scratch and use the TST instruction. (andsi3_cbranch, orrsi3_cbranch, xorsi3_cbranch, cbranchne_decr1) (addsi3_cbranch, subsi3_cbranch): Ensure that register preferencing cannot see high regs or memory alternatives. (bicsi3_cbranch_scratch, bicsi3_cbranch): New patterns. From-SVN: r72885
This commit is contained in:
Richard Earnshaw
parent
c21dbe8553
commit
c769a35d59
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@ -1,3 +1,28 @@
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2003-10-24 Richard Earnshaw <rearnsha@arm.com>
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* arm.c (arm_rtx_costs_1, case TARGET_THUMB): Adjust costs for
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comparing a constant with small negative numbers and add costing
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for constants in conjunction with AND.
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(note_invalid_constants): Tidy previous change.
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(thumb_cmp_operand): Tidy.
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(thumb_cmpneg_operand): New function.
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* arm.h (CONDITIONAL_REGISTER_USAGE): Don't use HI regs if optimizing
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for size.
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(FIRST_LO_REGNUM, FIRST_HI_REGNUM, LAST_HI_REGNUM): Define.
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(PREDICATE_CODES): Add thumb_cmpneg_operand.
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* arm.md (cbranchsi4): Convert to define_expand. Handle comparison
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with a negative constant.
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(cbranchsi4_insn): Matcher for cbranchsi4.
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(cbranchsi4_scratch): Similar, but a scratch is available for
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handling negative constants.
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(movsi_cbranchsi4): New pattern.
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(tstsi3_cbranch): Renamed from andsi3_cbranch_scratch, remove scratch
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and use the TST instruction.
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(andsi3_cbranch, orrsi3_cbranch, xorsi3_cbranch, cbranchne_decr1)
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(addsi3_cbranch, subsi3_cbranch): Ensure that register preferencing
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cannot see high regs or memory alternatives.
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(bicsi3_cbranch_scratch, bicsi3_cbranch): New patterns.
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2003-10-24 Richard Earnshaw <rearnsha@arm.com>
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* arm.c (note_invalid_constants): Try to extract the constant
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@ -119,8 +144,10 @@
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2003-10-22 Jan Hubicka <jh@suse.cz>
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* dwarf2out.c (dwarf2out_abstract_function): Use DW_AT to check presence of DW_AT_inline.
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(gen_subprogram_die): Likewise; do not abort instead of emitting DW_AT_not_inline
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* dwarf2out.c (dwarf2out_abstract_function): Use DW_AT to check
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presence of DW_AT_inline.
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(gen_subprogram_die): Likewise; do not abort instead of emitting
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DW_AT_not_inline.
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2003-10-22 Jan Hubicka <jh@suse.cz>
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@ -3131,12 +3131,12 @@ arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
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return COSTS_N_INSNS (2);
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return COSTS_N_INSNS (3);
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}
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else if (outer == PLUS
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else if ((outer == PLUS || outer == COMPARE)
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&& INTVAL (x) < 256 && INTVAL (x) > -256)
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return 0;
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else if (outer == COMPARE
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&& (unsigned HOST_WIDE_INT) INTVAL (x) < 256)
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return 0;
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return 0;
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else if (outer == AND
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&& INTVAL (x) < 256 && INTVAL (x) >= -256)
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return COSTS_N_INSNS (1);
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else if (outer == ASHIFT || outer == ASHIFTRT
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|| outer == LSHIFTRT)
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return 0;
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@ -6903,13 +6903,11 @@ note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
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us here. Lets just hope that we can use the
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constant pool value directly. */
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if (op == cop)
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op = get_pool_constant (XEXP (op, 0));
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else
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op = cop;
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cop = get_pool_constant (XEXP (op, 0));
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push_minipool_fix (insn, address,
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recog_data.operand_loc[opno],
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recog_data.operand_mode[opno], op);
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recog_data.operand_mode[opno], cop);
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}
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result = true;
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@ -12647,10 +12645,19 @@ int
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thumb_cmp_operand (rtx op, enum machine_mode mode)
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{
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return ((GET_CODE (op) == CONST_INT
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&& (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256)
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&& INTVAL (op) < 256
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&& INTVAL (op) >= 0)
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|| s_register_operand (op, mode));
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}
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int
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thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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return (GET_CODE (op) == CONST_INT
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&& INTVAL (op) < 0
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&& INTVAL (op) > -256);
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}
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/* Return TRUE if a result can be stored in OP without clobbering the
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condition code register. Prior to reload we only accept a
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register. After reload we have to be able to handle memory as
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@ -949,6 +949,16 @@ extern const char * structure_size_string;
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fixed_regs[regno] = call_used_regs[regno] = 1; \
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} \
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\
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if (TARGET_THUMB && optimize_size) \
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{ \
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/* When optimizing for size, it's better not to use \
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the HI regs, because of the overhead of stacking \
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them. */ \
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for (regno = FIRST_HI_REGNUM; \
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regno <= LAST_HI_REGNUM; ++regno) \
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fixed_regs[regno] = call_used_regs[regno] = 1; \
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} \
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\
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if (TARGET_CIRRUS) \
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{ \
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for (regno = FIRST_ARM_FP_REGNUM; \
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@ -1055,8 +1065,11 @@ extern const char * structure_size_string;
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/* The number of the last argument register. */
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#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
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/* The number of the last "lo" register (thumb). */
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/* The numbers of the Thumb register ranges. */
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#define FIRST_LO_REGNUM 0
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#define LAST_LO_REGNUM 7
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#define FIRST_HI_REGNUM 8
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#define LAST_HI_REGNUM 11
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/* The register that holds the return address in exception handlers. */
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#define EXCEPTION_LR_REGNUM 2
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@ -2693,6 +2706,7 @@ extern int making_const_table;
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{"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
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{"index_operand", {SUBREG, REG, CONST_INT}}, \
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{"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
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{"thumb_cmpneg_operand", {CONST_INT}}, \
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{"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \
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{"offsettable_memory_operand", {MEM}}, \
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{"bad_signed_byte_operand", {MEM}}, \
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@ -5209,17 +5209,36 @@
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;; For a 'b' pos_range = 2046, neg_range = -2048 giving (-2040->2048).
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;; For a 'b<cond>' pos_range = 254, neg_range = -256 giving (-250 ->256).
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(define_insn "cbranchsi4"
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[(set (pc)
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(if_then_else
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(match_operator 0 "arm_comparison_operator"
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[(match_operand:SI 1 "register_operand" "l,r")
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(match_operand:SI 2 "nonmemory_operand" "rI,r")])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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(define_expand "cbranchsi4"
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[(set (pc) (if_then_else
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(match_operator 0 "arm_comparison_operator"
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[(match_operand:SI 1 "s_register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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"TARGET_THUMB"
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"
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if (thumb_cmpneg_operand (operands[2], SImode))
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{
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emit_jump_insn (gen_cbranchsi4_scratch (NULL, operands[1], operands[2],
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operands[3], operands[0]));
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DONE;
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}
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if (!thumb_cmp_operand (operands[2], SImode))
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operands[2] = force_reg (SImode, operands[2]);
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")
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(define_insn "*cbranchsi4_insn"
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[(set (pc) (if_then_else
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(match_operator 0 "arm_comparison_operator"
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[(match_operand:SI 1 "s_register_operand" "l,*h")
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(match_operand:SI 2 "thumb_cmp_operand" "lI*h,*r")])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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"TARGET_THUMB"
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"*
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output_asm_insn (\"cmp\\t%1, %2\", operands);
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switch (get_attr_length (insn))
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{
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case 4: return \"b%d0\\t%l3\";
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@ -5244,13 +5263,111 @@
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(const_int 8))))]
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)
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(define_insn "cbranchsi4_scratch"
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[(set (pc) (if_then_else
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(match_operator 4 "arm_comparison_operator"
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[(match_operand:SI 1 "s_register_operand" "l,0")
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(match_operand:SI 2 "thumb_cmpneg_operand" "L,J")])
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(label_ref (match_operand 3 "" ""))
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(pc)))
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(clobber (match_scratch:SI 0 "=l,l"))]
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"TARGET_THUMB"
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"*
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output_asm_insn (\"add\\t%0, %1, #%n2\", operands);
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switch (get_attr_length (insn))
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{
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case 4: return \"b%d4\\t%l3\";
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case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\";
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default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\";
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}
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"
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[(set (attr "far_jump")
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(if_then_else
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(eq_attr "length" "8")
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(const_string "yes")
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(const_string "no")))
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(set (attr "length")
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(if_then_else
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(and (ge (minus (match_dup 3) (pc)) (const_int -250))
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(le (minus (match_dup 3) (pc)) (const_int 256)))
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(const_int 4)
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(if_then_else
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(and (ge (minus (match_dup 3) (pc)) (const_int -2040))
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(le (minus (match_dup 3) (pc)) (const_int 2048)))
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(const_int 6)
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(const_int 8))))]
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)
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(define_insn "*movsi_cbranchsi4"
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[(set (pc)
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(if_then_else
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(match_operator 3 "arm_comparison_operator"
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[(match_operand:SI 1 "s_register_operand" "0,l,l,l")
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(const_int 0)])
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(label_ref (match_operand 2 "" ""))
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(pc)))
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(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*h,*m")
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(match_dup 1))]
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"TARGET_THUMB"
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"*{
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if (which_alternative == 0)
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output_asm_insn (\"cmp\t%0, #0\", operands);
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else if (which_alternative == 1)
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output_asm_insn (\"sub\t%0, %1, #0\", operands);
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else
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{
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output_asm_insn (\"cmp\t%1, #0\", operands);
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if (which_alternative == 2)
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output_asm_insn (\"mov\t%0, %1\", operands);
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else
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output_asm_insn (\"str\t%1, %0\", operands);
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}
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switch (get_attr_length (insn) - ((which_alternative > 1) ? 2 : 0))
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{
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case 4: return \"b%d3\\t%l2\";
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case 6: return \"b%D3\\t.LCB%=\;b\\t%l2\\t%@long jump\\n.LCB%=:\";
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default: return \"b%D3\\t.LCB%=\;bl\\t%l2\\t%@far jump\\n.LCB%=:\";
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}
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}"
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[(set (attr "far_jump")
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(if_then_else
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(ior (and (gt (symbol_ref ("which_alternative"))
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(const_int 1))
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(eq_attr "length" "8"))
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(eq_attr "length" "10"))
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(const_string "yes")
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(const_string "no")))
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(set (attr "length")
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(if_then_else
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(le (symbol_ref ("which_alternative"))
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(const_int 1))
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(if_then_else
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(and (ge (minus (match_dup 2) (pc)) (const_int -250))
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(le (minus (match_dup 2) (pc)) (const_int 256)))
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(const_int 4)
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(if_then_else
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(and (ge (minus (match_dup 2) (pc)) (const_int -2040))
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(le (minus (match_dup 2) (pc)) (const_int 2048)))
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(const_int 6)
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(const_int 8)))
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(if_then_else
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(and (ge (minus (match_dup 2) (pc)) (const_int -248))
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(le (minus (match_dup 2) (pc)) (const_int 256)))
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(const_int 6)
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(if_then_else
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(and (ge (minus (match_dup 2) (pc)) (const_int -2038))
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(le (minus (match_dup 2) (pc)) (const_int 2048)))
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(const_int 8)
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(const_int 10)))))]
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)
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(define_insn "*negated_cbranchsi4"
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[(set (pc)
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(if_then_else
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(match_operator 0 "arm_comparison_operator"
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[(match_operand:SI 1 "register_operand" "l")
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(neg:SI (match_operand:SI 2 "nonmemory_operand" "l"))])
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(label_ref (match_operand 3 "" ""))
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(match_operator 0 "arm_comparison_operator"
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[(match_operand:SI 1 "s_register_operand" "l")
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(neg:SI (match_operand:SI 2 "s_register_operand" "l"))])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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"TARGET_THUMB"
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"*
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@ -5323,25 +5440,24 @@
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(const_int 8))))]
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)
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(define_insn "*andsi3_cbranch_scratch"
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(define_insn "*tstsi3_cbranch"
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[(set (pc)
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(if_then_else
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(match_operator 4 "equality_operator"
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[(and:SI (match_operand:SI 1 "s_register_operand" "%0")
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(match_operand:SI 2 "s_register_operand" "l"))
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(match_operator 3 "equality_operator"
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[(and:SI (match_operand:SI 0 "s_register_operand" "%l")
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(match_operand:SI 1 "s_register_operand" "l"))
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(const_int 0)])
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(label_ref (match_operand 3 "" ""))
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(pc)))
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(clobber (match_scratch:SI 0 "=l"))]
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(label_ref (match_operand 2 "" ""))
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(pc)))]
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"TARGET_THUMB"
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"*
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{
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output_asm_insn (\"and\\t%0, %2\", operands);
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output_asm_insn (\"tst\\t%0, %1\", operands);
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switch (get_attr_length (insn))
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{
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case 4: return \"b%d4\\t%l3\";
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case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\";
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default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\";
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case 4: return \"b%d3\\t%l2\";
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case 6: return \"b%D3\\t.LCB%=\;b\\t%l2\\t%@long jump\\n.LCB%=:\";
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default: return \"b%D3\\t.LCB%=\;bl\\t%l2\\t%@far jump\\n.LCB%=:\";
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}
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}"
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[(set (attr "far_jump")
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@ -5351,12 +5467,12 @@
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(const_string "no")))
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(set (attr "length")
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(if_then_else
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(and (ge (minus (match_dup 3) (pc)) (const_int -250))
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(le (minus (match_dup 3) (pc)) (const_int 256)))
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(and (ge (minus (match_dup 2) (pc)) (const_int -250))
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(le (minus (match_dup 2) (pc)) (const_int 256)))
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(const_int 4)
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(if_then_else
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(and (ge (minus (match_dup 3) (pc)) (const_int -2040))
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(le (minus (match_dup 3) (pc)) (const_int 2048)))
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(and (ge (minus (match_dup 2) (pc)) (const_int -2040))
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(le (minus (match_dup 2) (pc)) (const_int 2048)))
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(const_int 6)
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(const_int 8))))]
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)
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@ -5370,7 +5486,7 @@
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(const_int 0)])
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(label_ref (match_operand 4 "" ""))
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(pc)))
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(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,?h,?m,?m")
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(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m")
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(and:SI (match_dup 2) (match_dup 3)))
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(clobber (match_scratch:SI 1 "=X,l,&l,&l"))]
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"TARGET_THUMB"
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@ -5475,7 +5591,7 @@
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(const_int 0)])
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(label_ref (match_operand 4 "" ""))
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(pc)))
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(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,?h,?m,?m")
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(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m")
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(ior:SI (match_dup 2) (match_dup 3)))
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(clobber (match_scratch:SI 1 "=X,l,&l,&l"))]
|
||||
"TARGET_THUMB"
|
||||
|
|
@ -5580,7 +5696,7 @@
|
|||
(const_int 0)])
|
||||
(label_ref (match_operand 4 "" ""))
|
||||
(pc)))
|
||||
(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,?h,?m,?m")
|
||||
(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m")
|
||||
(xor:SI (match_dup 2) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 1 "=X,l,&l,&l"))]
|
||||
"TARGET_THUMB"
|
||||
|
|
@ -5638,6 +5754,111 @@
|
|||
(const_int 10)))))]
|
||||
)
|
||||
|
||||
(define_insn "*bicsi3_cbranch_scratch"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(match_operator 4 "equality_operator"
|
||||
[(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "l"))
|
||||
(match_operand:SI 1 "s_register_operand" "0"))
|
||||
(const_int 0)])
|
||||
(label_ref (match_operand 3 "" ""))
|
||||
(pc)))
|
||||
(clobber (match_scratch:SI 0 "=l"))]
|
||||
"TARGET_THUMB"
|
||||
"*
|
||||
{
|
||||
output_asm_insn (\"bic\\t%0, %2\", operands);
|
||||
switch (get_attr_length (insn))
|
||||
{
|
||||
case 4: return \"b%d4\\t%l3\";
|
||||
case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\";
|
||||
default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\";
|
||||
}
|
||||
}"
|
||||
[(set (attr "far_jump")
|
||||
(if_then_else
|
||||
(eq_attr "length" "8")
|
||||
(const_string "yes")
|
||||
(const_string "no")))
|
||||
(set (attr "length")
|
||||
(if_then_else
|
||||
(and (ge (minus (match_dup 3) (pc)) (const_int -250))
|
||||
(le (minus (match_dup 3) (pc)) (const_int 256)))
|
||||
(const_int 4)
|
||||
(if_then_else
|
||||
(and (ge (minus (match_dup 3) (pc)) (const_int -2040))
|
||||
(le (minus (match_dup 3) (pc)) (const_int 2048)))
|
||||
(const_int 6)
|
||||
(const_int 8))))]
|
||||
)
|
||||
|
||||
(define_insn "*bicsi3_cbranch"
|
||||
[(set (pc)
|
||||
(if_then_else
|
||||
(match_operator 5 "equality_operator"
|
||||
[(and:SI (not:SI (match_operand:SI 3 "s_register_operand" "l,l,l,l"))
|
||||
(match_operand:SI 2 "s_register_operand" "0,1,1,1"))
|
||||
(const_int 0)])
|
||||
(label_ref (match_operand 4 "" ""))
|
||||
(pc)))
|
||||
(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m")
|
||||
(and:SI (not:SI (match_dup 3)) (match_dup 2)))
|
||||
(clobber (match_scratch:SI 1 "=X,l,&l,&l"))]
|
||||
"TARGET_THUMB"
|
||||
"*
|
||||
{
|
||||
if (which_alternative == 0)
|
||||
output_asm_insn (\"bic\\t%0, %3\", operands);
|
||||
else if (which_alternative == 1)
|
||||
{
|
||||
output_asm_insn (\"bic\\t%1, %3\", operands);
|
||||
output_asm_insn (\"mov\\t%0, %1\", operands);
|
||||
}
|
||||
else
|
||||
{
|
||||
output_asm_insn (\"bic\\t%1, %3\", operands);
|
||||
output_asm_insn (\"str\\t%1, %0\", operands);
|
||||
}
|
||||
|
||||
switch (get_attr_length (insn) - (which_alternative ? 2 : 0))
|
||||
{
|
||||
case 4: return \"b%d5\\t%l4\";
|
||||
case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\";
|
||||
default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\";
|
||||
}
|
||||
}"
|
||||
[(set (attr "far_jump")
|
||||
(if_then_else
|
||||
(ior (and (eq (symbol_ref ("which_alternative"))
|
||||
(const_int 0))
|
||||
(eq_attr "length" "8"))
|
||||
(eq_attr "length" "10"))
|
||||
(const_string "yes")
|
||||
(const_string "no")))
|
||||
(set (attr "length")
|
||||
(if_then_else
|
||||
(eq (symbol_ref ("which_alternative"))
|
||||
(const_int 0))
|
||||
(if_then_else
|
||||
(and (ge (minus (match_dup 4) (pc)) (const_int -250))
|
||||
(le (minus (match_dup 4) (pc)) (const_int 256)))
|
||||
(const_int 4)
|
||||
(if_then_else
|
||||
(and (ge (minus (match_dup 4) (pc)) (const_int -2040))
|
||||
(le (minus (match_dup 4) (pc)) (const_int 2048)))
|
||||
(const_int 6)
|
||||
(const_int 8)))
|
||||
(if_then_else
|
||||
(and (ge (minus (match_dup 4) (pc)) (const_int -248))
|
||||
(le (minus (match_dup 4) (pc)) (const_int 256)))
|
||||
(const_int 6)
|
||||
(if_then_else
|
||||
(and (ge (minus (match_dup 4) (pc)) (const_int -2038))
|
||||
(le (minus (match_dup 4) (pc)) (const_int 2048)))
|
||||
(const_int 8)
|
||||
(const_int 10)))))]
|
||||
)
|
||||
|
||||
(define_insn "*cbranchne_decr1"
|
||||
[(set (pc)
|
||||
(if_then_else (match_operator 3 "equality_operator"
|
||||
|
|
@ -5645,7 +5866,7 @@
|
|||
(const_int 0)])
|
||||
(label_ref (match_operand 4 "" ""))
|
||||
(pc)))
|
||||
(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,?h,?m,?m")
|
||||
(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m")
|
||||
(plus:SI (match_dup 2) (const_int -1)))
|
||||
(clobber (match_scratch:SI 1 "=X,l,&l,&l"))]
|
||||
"TARGET_THUMB"
|
||||
|
|
@ -5751,8 +5972,9 @@
|
|||
(const_int 0)])
|
||||
(label_ref (match_operand 5 "" ""))
|
||||
(pc)))
|
||||
(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,?h,?m,?m")
|
||||
(plus:SI (match_dup 2) (match_dup 3)))
|
||||
(set
|
||||
(match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m")
|
||||
(plus:SI (match_dup 2) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 1 "=X,X,X,l,&l,&l"))]
|
||||
"TARGET_THUMB
|
||||
&& (GET_CODE (operands[4]) == EQ
|
||||
|
|
@ -5894,7 +6116,7 @@
|
|||
(const_int 0)])
|
||||
(label_ref (match_operand 5 "" ""))
|
||||
(pc)))
|
||||
(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,?h,?m,?m")
|
||||
(set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m")
|
||||
(minus:SI (match_dup 2) (match_dup 3)))
|
||||
(clobber (match_scratch:SI 1 "=X,l,&l,&l"))]
|
||||
"TARGET_THUMB
|
||||
|
|
|
|||
Loading…
Reference in New Issue