peep2-xsrand.c, [...]: Drop redundant target-specifier.
* gcc.target/cris/peep2-xsrand.c, gcc.target/cris/asmreg-1.c, gcc.target/cris/peep2-andu1.c, gcc.target/cris/peep2-xsrand2.c, gcc.target/cris/20011127-1.c: Drop redundant target-specifier. * gcc.target/cris/peep2-andu2.c: Ditto. Make dg-do assemble and add -save-temps. * gcc.target/cris/torture/cris-torture.exp, gcc.target/cris/cris.exp: Run for crisv32-*-* too. * gcc.target/cris/builtin_ctz_v3.c, gcc.target/cris/builtin_ctz_v8.c, gcc.target/cris/builtin_clz_v0.c, gcc.target/cris/builtin_clz_v3.c, gcc.target/cris/builtin_bswap_v3.c, gcc.target/cris/builtin_bswap_v8.c, gcc.dg/sibcall-4.c, gcc.dg/pr19340.c, gcc.dg/20020919-1.c, gcc.dg/pr31866.c, gcc.dg/torture/cris-asm-mof-1.c, gcc.dg/torture/cris-volatile-1.c, gcc.dg/weak/typeof-2.c, gcc.dg/tree-ssa/loop-1.c, gcc.dg/tree-ssa/20040204-1.c, gcc.dg/sibcall-3.c, lib/target-supports.exp: Adjust for crisv32-*-*. From-SVN: r130962
This commit is contained in:
parent
a2e51f7753
commit
c7e30cf2d1
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@ -1,3 +1,24 @@
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2007-12-15 Hans-Peter Nilsson <hp@axis.com>
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* gcc.target/cris/peep2-xsrand.c, gcc.target/cris/asmreg-1.c,
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gcc.target/cris/peep2-andu1.c, gcc.target/cris/peep2-xsrand2.c,
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gcc.target/cris/20011127-1.c: Drop redundant target-specifier.
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* gcc.target/cris/peep2-andu2.c: Ditto. Make dg-do assemble and
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add -save-temps.
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* gcc.target/cris/torture/cris-torture.exp,
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gcc.target/cris/cris.exp: Run for crisv32-*-* too.
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* gcc.target/cris/builtin_ctz_v3.c,
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gcc.target/cris/builtin_ctz_v8.c,
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gcc.target/cris/builtin_clz_v0.c,
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gcc.target/cris/builtin_clz_v3.c,
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gcc.target/cris/builtin_bswap_v3.c,
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gcc.target/cris/builtin_bswap_v8.c, gcc.dg/sibcall-4.c,
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gcc.dg/pr19340.c, gcc.dg/20020919-1.c, gcc.dg/pr31866.c,
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gcc.dg/torture/cris-asm-mof-1.c, gcc.dg/torture/cris-volatile-1.c,
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gcc.dg/weak/typeof-2.c, gcc.dg/tree-ssa/loop-1.c,
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gcc.dg/tree-ssa/20040204-1.c, gcc.dg/sibcall-3.c,
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lib/target-supports.exp: Adjust for crisv32-*-*.
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2007-12-15 Alexandre Oliva <aoliva@redhat.com>
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* gcc.dg/debug/const-3.c: New.
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@ -8,7 +8,7 @@
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You must be this tall ---> fit two long longs in asm-declared registers
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to enter this amusement. */
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/* { dg-do compile { target alpha-*-* cris-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */
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/* { dg-do compile { target alpha-*-* cris-*-* crisv32-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */
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/* { dg-options "-O2" } */
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/* Constructed examples; input/output (same register), output, input, and
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@ -1,6 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-O1 -fschedule-insns2 -fsched2-use-traces" } */
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/* { dg-skip-if "No scheduling" { mmix-*-* cris-*-* fido-*-* m68k-*-* m32c-*-* } { "*" } { "" } } */
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/* { dg-skip-if "No scheduling" { mmix-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* m32c-*-* } { "*" } { "" } } */
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extern double f (double x);
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@ -1,5 +1,5 @@
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/* PR tree-optimization/31866 */
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/* { dg-do compile { target alpha-*-* cris-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */
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/* { dg-do compile { target alpha-*-* cris-*-* crisv32-*-* i?86-*-* mmix-*-* powerpc*-*-* rs6000-*-* x86_64-*-* } } */
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/* { dg-options "-O2" } */
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#if defined (__alpha__)
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@ -5,7 +5,7 @@
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Copyright (C) 2002 Free Software Foundation Inc.
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Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
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/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
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/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
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/* -mlongcall disables sibcall patterns. */
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/* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
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/* { dg-options "-O2 -foptimize-sibling-calls" } */
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@ -5,7 +5,7 @@
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Copyright (C) 2002 Free Software Foundation Inc.
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Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
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/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
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/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
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/* -mlongcall disables sibcall patterns. */
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/* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
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/* { dg-options "-O2 -foptimize-sibling-calls" } */
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@ -1,5 +1,5 @@
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/* { dg-do compile { target cris-*-* } } */
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/* { dg-skip-if "" { cris-*-* } { "-march*" } { "" } } */
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/* { dg-do compile { target cris-*-* crisv32-*-* } } */
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/* { dg-skip-if "" { cris*-*-* } { "-march*" } { "" } } */
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/* { dg-options "-O2 -march=v10" } */
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/* { dg-final { scan-assembler "in-asm: .mof" } } */
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/* { dg-final { scan-assembler "out-asm: .mof" } } */
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@ -2,7 +2,7 @@
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Check that size-optimizations for move insns (specifically peephole
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optimizations) aren't applied to volatile objects in the CRIS port.
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Origin: Hans-Peter Nilsson. */
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/* { dg-do compile { target cris-*-* } } */
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/* { dg-do compile { target cris-*-* crisv32-*-* } } */
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/* { dg-final { scan-assembler-not {movu\...\[} } } */
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/* { dg-final { scan-assembler-not {move\.[^d].\[} } } */
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/* { dg-final { scan-assembler-not {and\.[^d].\[} } } */
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@ -33,5 +33,5 @@ void test55 (int x, int y)
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that the && should be emitted (based on BRANCH_COST). Fix this
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by teaching dom to look through && and register all components
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as true. */
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/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "powerpc*-*-* cris-*-* mmix-*-* mips*-*-*" } } } } */
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/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { ! "powerpc*-*-* cris-*-* crisv32-*-* mmix-*-* mips*-*-*" } } } } */
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/* { dg-final { cleanup-tree-dump "optimized" } } */
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@ -39,7 +39,7 @@ void xxx(void)
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/* CRIS keeps the address in a register. */
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/* m68k sometimes puts the address in a register, depending on CPU and PIC. */
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/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* fido-*-* m68k-*-* } } } */
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/* { dg-final { scan-assembler-times "foo" 5 { xfail hppa*-*-* ia64*-*-* sh*-*-* cris-*-* crisv32-*-* fido-*-* m68k-*-* } } } */
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/* { dg-final { scan-assembler-times "foo,%r" 5 { target hppa*-*-* } } } */
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/* { dg-final { scan-assembler-times "= foo" 5 { target ia64*-*-* } } } */
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/* { dg-final { scan-assembler-times "jsr|bsrf|blink\ttr?,r18" 5 { target sh*-*-* } } } */
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// { dg-final { if [string match s390*-*-* $target_triplet ] {return} } }
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// Likewise for CRIS targets.
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// { dg-final { if [string match cris-*-* $target_triplet ] {return} } }
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// { dg-final { if [string match crisv32-*-* $target_triplet ] {return} } }
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// Likewise for m68k targets.
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// { dg-final { if [string match fido-*-* $target_triplet ] {return} } }
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// { dg-final { if [string match m68k-*-* $target_triplet ] {return} } }
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Making sure that invalid asm operand modifiers don't cause an ICE. */
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/* { dg-do compile { target cris-*-* } } */
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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/* { dg-message "reg:SI|const_double:DF" "prune debug_rtx output" { target cris-*-* } 0 } */
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/* { dg-message "reg:SI|const_double:DF" "prune debug_rtx output" { target *-*-* } 0 } */
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void
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foo (void)
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/* { dg-do compile { target cris-*-* } } */
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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/* { dg-final { scan-assembler "\\\.ifnc \\\$r9-\\\$r10-\\\$r11-\\\$r12" } } */
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/* Check that we don't use the swap insn for bswap by checking assembler
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output. The swap instruction was added in v8. */
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/* { dg-do compile } */
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/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
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/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
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/* { dg-options "-O2 -march=v3" } */
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/* { dg-final { scan-assembler-not "\[ \t\]swapwb\[ \t\]" } } */
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/* Check that we use the swap insn for bswap by checking assembler
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output. The swap instruction was added in v8. */
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/* { dg-do compile } */
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/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
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/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
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/* { dg-options "-O2 -march=v8" } */
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/* { dg-final { scan-assembler "\[ \t\]swapwb\[ \t\]" } } */
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/* Check that we don't use the lz insn for clz by checking assembler output.
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The lz insn was implemented in CRIS v3 (ETRAX 4). */
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/* { dg-do compile } */
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/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
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/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
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/* { dg-options "-O2 -march=v0" } */
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/* { dg-final { scan-assembler-not "\[ \t\]lz\[ \t\]" } } */
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/* Check that we use the lz insn for clz by checking assembler output.
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The lz insn was implemented in CRIS v3 (ETRAX 4). */
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/* { dg-do compile } */
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/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
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/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
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/* { dg-options "-O2 -march=v3" } */
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/* { dg-final { scan-assembler "\[ \t\]lz\[ \t\]" } } */
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/* Check that we don't use the swap insn for ctz by checking
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assembler output. The swap instruction was implemented in v8. */
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/* { dg-do compile } */
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/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
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/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
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/* { dg-options "-O2 -march=v3" } */
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/* { dg-final { scan-assembler-not "\[ \t\]swapwbr\[ \t\]" } } */
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/* Check that we use the swap insn for ctz by checking assembler output.
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The swap instruction was implemented in v8. */
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/* { dg-do compile } */
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/* { dg-skip-if "" { "cris-*-elf" } { "-march*" } { "" } } */
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/* { dg-skip-if "" { "cris*-*-elf" } { "-march*" } { "" } } */
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/* { dg-options "-O2 -march=v8" } */
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/* { dg-final { scan-assembler "\[ \t\]swapwbr\[ \t\]" } } */
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# looping over tests.
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# Exit immediately if this isn't a CRIS target.
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if ![istarget cris-*-*] then {
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if { ![istarget cris-*-*] && ![istarget crisv32-*-*] } then {
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return
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}
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/* { dg-do compile { target cris-*-* } } */
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/* { dg-do compile } */
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/* { dg-final { scan-assembler-not "and.d " } } */
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/* { dg-final { scan-assembler-not "move.d " } } */
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/* { dg-final { scan-assembler "cLear.b" } } */
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/* { dg-do compile { target cris-*-* } } */
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/* { dg-final { scan-assembler "movu.w \\\$r10,\\\$r" } } */
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/* { dg-final { scan-assembler "and.w 2047,\\\$r" } } */
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/* { dg-final { scan-assembler-not "move.d \\\$r10,\\\$r" } } */
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/* { dg-final { scan-assembler "movu.b \\\$r10,\\\$r" } } */
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/* { dg-final { scan-assembler "and.b 95,\\\$r" } } */
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/* { dg-final { scan-assembler "andq -2,\\\$r" } } */
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/* { dg-options "-O2" } */
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/* { dg-do assemble } */
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/* { dg-final { scan-assembler "movu.w \\\$r10,\\\$" } } */
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/* { dg-final { scan-assembler "and.w 2047,\\\$" } } */
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/* { dg-final { scan-assembler-not "move.d \\\$r10,\\\$" } } */
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/* { dg-final { scan-assembler "movu.b \\\$r10,\\\$" } } */
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/* { dg-final { scan-assembler "and.b 95,\\\$" } } */
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/* { dg-final { scan-assembler "andq -2,\\\$" } } */
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/* { dg-options "-O2 -save-temps" } */
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/* Test the "andu" peephole2 trivially, register operand. */
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/* { dg-do compile { target cris-*-* } } */
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/* { dg-do compile } */
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/* { dg-final { scan-assembler "and.w " } } */
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/* { dg-final { scan-assembler "and.b " } } */
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/* { dg-final { scan-assembler-not "and.d" } } */
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/* { dg-do compile { target cris-*-* } } */
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/* { dg-do compile } */
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/* { dg-final { scan-assembler "and.w -137," } } */
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/* { dg-final { scan-assembler "and.b -64," } } */
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/* { dg-final { scan-assembler "and.w -139," } } */
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# optimization options.
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# Exit immediately if this isn't a CRIS target.
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if ![istarget cris-*-*] then {
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if { ![istarget cris-*-*] && ![istarget crisv32-*-*] } then {
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return
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}
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@ -421,6 +421,7 @@ proc check_profiling_available { test_what } {
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|| [istarget strongarm*-*-elf]
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|| [istarget xscale*-*-elf]
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|| [istarget cris-*-*]
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|| [istarget crisv32-*-*]
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|| [istarget fido-*-elf]
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|| [istarget h8300-*-*]
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|| [istarget m32c-*-elf]
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Reference in New Issue