mips.md: Add combiner patterns for DImode extensions of HImode and QImode truncations.
gcc/ * config/mips/mips.md: Add combiner patterns for DImode extensions of HImode and QImode truncations. Reformat HImode <- QImode pattern for consistency. From-SVN: r129695
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@ -1,3 +1,9 @@
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2007-10-28 Richard Sandiford <rsandifo@nildram.co.uk>
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* config/mips/mips.md: Add combiner patterns for DImode extensions
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of HImode and QImode truncations. Reformat HImode <- QImode pattern
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for consistency.
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2007-10-28 Richard Sandiford <rsandifo@nildram.co.uk>
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PR target/33895
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@ -2366,68 +2366,73 @@
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(set_attr "mode" "SI")])
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;; Combiner patterns for truncate/sign_extend combinations. They use
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;; the shift/truncate patterns above.
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;; Combiner patterns for truncate/sign_extend combinations. The SI versions
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;; use the shift/truncate patterns above.
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(define_insn_and_split ""
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[(set (match_operand:SI 0 "register_operand" "=d")
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(sign_extend:SI
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(truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
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(define_insn_and_split "*extenddi_truncate<mode>"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(sign_extend:DI
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(truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
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"TARGET_64BIT && !TARGET_MIPS16"
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"#"
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"&& reload_completed"
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[(set (match_dup 2)
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(ashift:DI (match_dup 1)
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(const_int 48)))
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(match_dup 3)))
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(set (match_dup 0)
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(truncate:SI (ashiftrt:DI (match_dup 2)
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(const_int 48))))]
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{ operands[2] = gen_lowpart (DImode, operands[0]); })
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(ashiftrt:DI (match_dup 2)
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(match_dup 3)))]
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{
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operands[2] = gen_lowpart (DImode, operands[0]);
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operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
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})
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(define_insn_and_split ""
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(define_insn_and_split "*extendsi_truncate<mode>"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(sign_extend:SI
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(truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
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(truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
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"TARGET_64BIT && !TARGET_MIPS16"
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"#"
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"&& reload_completed"
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[(set (match_dup 2)
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(ashift:DI (match_dup 1)
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(const_int 56)))
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(match_dup 3)))
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(set (match_dup 0)
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(truncate:SI (ashiftrt:DI (match_dup 2)
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(const_int 56))))]
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{ operands[2] = gen_lowpart (DImode, operands[0]); })
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(match_dup 3))))]
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{
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operands[2] = gen_lowpart (DImode, operands[0]);
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operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
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})
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;; Combiner patterns to optimize truncate/zero_extend combinations.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=d")
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(zero_extend:SI (truncate:HI
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(match_operand:DI 1 "register_operand" "d"))))]
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(define_insn "*zero_extend<mode>_trunchi"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(zero_extend:GPR
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(truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
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"TARGET_64BIT && !TARGET_MIPS16"
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"andi\t%0,%1,0xffff"
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[(set_attr "type" "logical")
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(set_attr "mode" "SI")])
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[(set_attr "type" "logical")
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(set_attr "mode" "<MODE>")])
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=d")
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(zero_extend:SI (truncate:QI
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(match_operand:DI 1 "register_operand" "d"))))]
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(define_insn "*zero_extend<mode>_truncqi"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(zero_extend:GPR
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(truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
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"TARGET_64BIT && !TARGET_MIPS16"
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"andi\t%0,%1,0xff"
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[(set_attr "type" "logical")
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(set_attr "mode" "SI")])
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[(set_attr "type" "logical")
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(set_attr "mode" "<MODE>")])
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(define_insn ""
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[(set (match_operand:HI 0 "register_operand" "=d")
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(zero_extend:HI (truncate:QI
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(match_operand:DI 1 "register_operand" "d"))))]
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(zero_extend:HI
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(truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
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"TARGET_64BIT && !TARGET_MIPS16"
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"andi\t%0,%1,0xff"
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[(set_attr "type" "logical")
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(set_attr "mode" "HI")])
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[(set_attr "type" "logical")
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(set_attr "mode" "HI")])
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;;
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;; ....................
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