coff.h: Replace Hitachi with Renesas.

* config/sh/coff.h: Replace Hitachi with Renesas.
	* config/sh/elf.h: Likewise.
	* config/sh/embed-elf.h: Likewise.
	* config/sh/lib1funcs.asm: Likewise.
	* config/sh/sh-protos.h: Likewise.
	* config/sh/sh.c: Likewise.
	* config/sh/sh.h: Likewise.
	* config/sh/sh.md: Likewise.

From-SVN: r68107
This commit is contained in:
Kazu Hirata 2003-06-17 19:19:16 +00:00 committed by Kazu Hirata
parent 7d8f4ff955
commit c8f0269d46
9 changed files with 28 additions and 17 deletions

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@ -1,3 +1,14 @@
2003-06-17 Kazu Hirata <kazu@cs.umass.edu>
* config/sh/coff.h: Replace Hitachi with Renesas.
* config/sh/elf.h: Likewise.
* config/sh/embed-elf.h: Likewise.
* config/sh/lib1funcs.asm: Likewise.
* config/sh/sh-protos.h: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.h: Likewise.
* config/sh/sh.md: Likewise.
2003-06-17 Kazu Hirata <kazu@cs.umass.edu>
* ChangeLog.3: Fix comment typos.

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@ -1,4 +1,4 @@
/* Definitions of target machine for gcc for Hitachi / SuperH SH using ELF.
/* Definitions of target machine for gcc for Renesas / SuperH SH using ELF.
Copyright (C) 1997, 1998, 2001, 2002 Free Software Foundation, Inc.
Contributed by Jörn Rennecke <joern.rennecke@superh.com>.

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@ -1,4 +1,4 @@
/* Definitions of target machine for gcc for Hitachi / SuperH SH using ELF.
/* Definitions of target machine for gcc for Renesas / SuperH SH using ELF.
Copyright (C) 1996, 1997, 2000, 2001, 2002 Free Software Foundation, Inc.
Contributed by Ian Lance Taylor <ian@cygnus.com>.

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@ -1,4 +1,4 @@
/* Definitions of target machine for GNU compiler for Hitachi / SuperH SH
/* Definitions of target machine for GNU compiler for Renesas / SuperH SH
non-Linux embedded targets.
Copyright (C) 2002 Free Software Foundation, Inc.
Contributed by J"orn Rennecke <joern.rennecke@superh.com>

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@ -25,7 +25,7 @@ along with this program; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
!! libgcc routines for the Hitachi / SuperH SH CPUs.
!! libgcc routines for the Renesas / SuperH SH CPUs.
!! Contributed by Steve Chamberlain.
!! sac@cygnus.com
@ -998,7 +998,7 @@ hiset: sts macl,r0 ! r0 = bb*dd
#endif /* ! __SH5__ */
#ifdef L_sdivsi3_i4
.title "SH DIVIDE"
!! 4 byte integer Divide code for the Hitachi SH
!! 4 byte integer Divide code for the Renesas SH
#ifdef __SH4__
!! args in r4 and r5, result in fpul, clobber dr0, dr2
@ -1306,7 +1306,7 @@ div0: rts
#ifdef L_udivsi3_i4
.title "SH DIVIDE"
!! 4 byte integer Divide code for the Hitachi SH
!! 4 byte integer Divide code for the Renesas SH
#ifdef __SH4__
!! args in r4 and r5, result in fpul, clobber r0, r1, r4, r5, dr0, dr2, dr4,
!! and t bit

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@ -1,4 +1,4 @@
/* Definitions of target machine for GNU compiler for Hitachi / SuperH SH.
/* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003
Free Software Foundation, Inc.
Contributed by Steve Chamberlain (sac@cygnus.com).

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@ -1,4 +1,4 @@
/* Output routines for GCC for Hitachi / SuperH SH.
/* Output routines for GCC for Renesas / SuperH SH.
Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002,
2003 Free Software Foundation, Inc.
Contributed by Steve Chamberlain (sac@cygnus.com).
@ -6047,7 +6047,7 @@ initial_elimination_offset (from, to)
abort ();
}
/* Handle machine specific pragmas to be semi-compatible with Hitachi
/* Handle machine specific pragmas to be semi-compatible with Renesas
compiler. */
void

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@ -1,4 +1,4 @@
/* Definitions of target machine for GNU compiler for Hitachi / SuperH SH.
/* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
2003 Free Software Foundation, Inc.
Contributed by Steve Chamberlain (sac@cygnus.com).
@ -102,7 +102,7 @@ do { \
} \
if (flag_pic) \
fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
/* Hitachi saves and restores mac registers on call. */ \
/* Renesas saves and restores mac registers on call. */ \
if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
{ \
call_used_regs[MACH_REG] = 0; \
@ -235,14 +235,14 @@ extern int target_flags;
to do function call relaxing. */
#define TARGET_RELAX (target_flags & RELAX_BIT)
/* Nonzero if using Hitachi's calling convention. */
/* Nonzero if using Renesas's calling convention. */
#define TARGET_HITACHI (target_flags & HITACHI_BIT)
/* Nonzero if not saving macl/mach when using -mhitachi */
#define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
/* Nonzero if padding structures to a multiple of 4 bytes. This is
incompatible with Hitachi's compiler, and gives unusual structure layouts
incompatible with Renesas's compiler, and gives unusual structure layouts
which confuse programmers.
??? This option is not useful, but is retained in case there are people
who are still relying on it. It may be deleted in the future. */
@ -682,7 +682,7 @@ do { \
/* Standard register usage. */
/* Register allocation for the Hitachi calling convention:
/* Register allocation for the Renesas calling convention:
r0 arg return
r1..r3 scratch
@ -1119,7 +1119,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
where the address is passed. If it returns 0, the address is
passed as an "invisible" first argument. */
/* The Hitachi calling convention doesn't quite fit into this scheme since
/* The Renesas calling convention doesn't quite fit into this scheme since
the address is passed like an invisible argument, but one that is always
passed in memory. */
#define STRUCT_VALUE \
@ -3280,7 +3280,7 @@ extern enum mdep_reorg_phase_e mdep_reorg_phase;
#define TARGET_MEM_FUNCTIONS
/* Handle Hitachi compiler's pragmas. */
/* Handle Renesas compiler's pragmas. */
#define REGISTER_TARGET_PRAGMAS() do { \
c_register_pragma (0, "interrupt", sh_pr_interrupt); \
c_register_pragma (0, "trapa", sh_pr_trapa); \

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@ -1,4 +1,4 @@
;;- Machine description for Hitachi / SuperH SH.
;;- Machine description for Renesas / SuperH SH.
;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
;; Free Software Foundation, Inc.
;; Contributed by Steve Chamberlain (sac@cygnus.com).