cmp_fp_op.inc: New file.
2014-10-24 Christophe Lyon <christophe.lyon@linaro.org> * gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vcage.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcagt.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcale.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vcalt.c: Likewise. From-SVN: r216645
This commit is contained in:
Christophe Lyon
Christophe Lyon
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commit
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@ -1,3 +1,11 @@
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2014-10-24 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc: New file.
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* gcc.target/aarch64/advsimd-intrinsics/vcage.c: Likewise.
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* gcc.target/aarch64/advsimd-intrinsics/vcagt.c: Likewise.
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* gcc.target/aarch64/advsimd-intrinsics/vcale.c: Likewise.
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* gcc.target/aarch64/advsimd-intrinsics/vcalt.c: Likewise.
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2014-10-24 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc: New file.
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@ -0,0 +1,75 @@
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/* Template file for the validation of comparison operator with
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floating-point support.
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This file is meant to be included by the relevant test files, which
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have to define the intrinsic family to test. If a given intrinsic
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supports variants which are not supported by all the other
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operators, these can be tested by providing a definition for
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EXTRA_TESTS. */
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#include <arm_neon.h>
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#include "arm-neon-ref.h"
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#include "compute-ref-data.h"
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/* Additional expected results declaration, they are initialized in
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each test file. */
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extern ARRAY(expected2, uint, 32, 2);
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extern ARRAY(expected2, uint, 32, 4);
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#define FNNAME1(NAME) exec_ ## NAME
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#define FNNAME(NAME) FNNAME1(NAME)
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void FNNAME (INSN_NAME) (void)
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{
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/* Basic test: y=vcomp(x1,x2), then store the result. */
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#define TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N) \
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VECT_VAR(vector_res, T3, W, N) = \
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INSN##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
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VECT_VAR(vector2, T1, W, N)); \
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vst1##Q##_u##W(VECT_VAR(result, T3, W, N), VECT_VAR(vector_res, T3, W, N))
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#define TEST_VCOMP(INSN, Q, T1, T2, T3, W, N) \
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TEST_VCOMP1(INSN, Q, T1, T2, T3, W, N)
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DECL_VARIABLE(vector, float, 32, 2);
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DECL_VARIABLE(vector, float, 32, 4);
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DECL_VARIABLE(vector2, float, 32, 2);
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DECL_VARIABLE(vector2, float, 32, 4);
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DECL_VARIABLE(vector_res, uint, 32, 2);
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DECL_VARIABLE(vector_res, uint, 32, 4);
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clean_results ();
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/* Initialize input "vector" from "buffer". */
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VLOAD(vector, buffer, , float, f, 32, 2);
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VLOAD(vector, buffer, q, float, f, 32, 4);
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/* Choose init value arbitrarily, will be used for vector
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comparison. */
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VDUP(vector2, , float, f, 32, 2, -16.0f);
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VDUP(vector2, q, float, f, 32, 4, -14.0f);
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/* Apply operator named INSN_NAME. */
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TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2);
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CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
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TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4);
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CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
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/* Test again, with different input values. */
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VDUP(vector2, , float, f, 32, 2, -10.0f);
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VDUP(vector2, q, float, f, 32, 4, 10.0f);
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TEST_VCOMP(INSN_NAME, , float, f, uint, 32, 2);
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CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected2, "");
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TEST_VCOMP(INSN_NAME, q, float, f, uint, 32, 4);
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CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected2,"");
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}
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int main (void)
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{
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FNNAME (INSN_NAME) ();
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return 0;
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}
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52
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c
Normal file
52
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcage.c
Normal file
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#define INSN_NAME vcage
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#define TEST_MSG "VCAGE/VCAGEQ"
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#include "cmp_fp_op.inc"
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/* Expected results. */
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VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
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VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0x0 };
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VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
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VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333,
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0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333,
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0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
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0x3333333333333333 };
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VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333,
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0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff,
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0xffffffff, 0x0 };
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VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
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0x3333333333333333 };
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VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
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0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
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0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff };
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VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff };
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51
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c
Normal file
51
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcagt.c
Normal file
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#define INSN_NAME vcagt
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#define TEST_MSG "VCAGT/VCAGTQ"
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#include "cmp_fp_op.inc"
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/* Expected results. */
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VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
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VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0x0 };
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VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
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VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333,
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0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 };
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VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
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0x3333333333333333 };
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VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333,
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0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffffff, 0xffffffff,
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0x0, 0x0 };
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VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
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0x3333333333333333 };
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VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
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0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
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0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xffffffff, 0xffffffff };
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VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff };
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49
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c
Normal file
49
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcale.c
Normal file
@ -0,0 +1,49 @@
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#define INSN_NAME vcale
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#define TEST_MSG "VCALE/VCALEQ"
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#include "cmp_fp_op.inc"
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/* Expected results. */
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VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
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VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffffff, 0xffffffff };
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VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
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VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333,
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0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 };
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VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
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0x3333333333333333 };
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VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333,
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0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0xffffffff, 0xffffffff };
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VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
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0x3333333333333333 };
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VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
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0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
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0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 };
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VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
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49
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c
Normal file
49
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcalt.c
Normal file
@ -0,0 +1,49 @@
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#define INSN_NAME vcalt
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#define TEST_MSG "VCALT/VCALTQ"
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#include "cmp_fp_op.inc"
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/* Expected results. */
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VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,int,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 };
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VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,uint,16,4) [] = { 0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,uint,32,2) [] = { 0x0, 0xffffffff };
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VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 };
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VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 };
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VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,int,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333,
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0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffffff, 0xffffffff, 0x0, 0x0 };
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VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333,
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0x3333333333333333 };
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VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,uint,16,8) [] = { 0x333, 0x3333, 0x3333, 0x3333,
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0x333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,uint,32,4) [] = { 0x0, 0x0, 0x0, 0xffffffff };
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VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333,
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0x3333333333333333 };
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VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33,
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0x33, 0x33, 0x33, 0x33 };
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VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333,
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0x3333, 0x3333, 0x3333, 0x3333 };
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VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333,
|
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0x33333333, 0x33333333 };
|
||||
|
||||
VECT_VAR_DECL(expected2,uint,32,2) [] = { 0x0, 0x0 };
|
||||
VECT_VAR_DECL(expected2,uint,32,4) [] = { 0x0, 0x0, 0x0, 0x0 };
|
||||
Loading…
Reference in New Issue
Block a user