config.gcc: Support "knm".
gcc/
* config.gcc: Support "knm".
* config/i386/driver-i386.c (host_detect_local_cpu): Detect "knm".
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
PROCESSOR_KNM.
* config/i386/i386.c (m_KNM): Define.
(processor_target_table): Add "knm".
(PTA_KNM): Define.
(ix86_option_override_internal): Add "knm".
(ix86_issue_rate): Add PROCESSOR_KNM.
(ix86_adjust_cost): Ditto.
(ia32_multipass_dfa_lookahead): Ditto.
(get_builtin_code_for_version): Handle PROCESSOR_KNM.
(fold_builtin_cpu): Add M_INTEL_KNM.
* config/i386/i386.h (processor_costs): Define TARGET_KNM.
(processor_type): Add PROCESSOR_KNM.
* config/i386/x86-tune.def: Add m_KNM.
* doc/invoke.texi: Add knm as x86 -march=/-mtune= CPU type.
libgcc/
* config/i386/cpuinfo.h (processor_types): Add INTEL_KNM.
* config/i386/cpuinfo.c (get_intel_cpu): Detect Knights Mill.
gcc/testsuite/
* gcc.target/i386/builtin_target.c: Test knm.
* gcc.target/i386/funcspec-56.inc: Test arch=knm.
From-SVN: r253013
This commit is contained in:
Sebastian Peryt
Uros Bizjak
parent
2288ea2381
commit
cace2309d4
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@ -1,3 +1,23 @@
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2017-09-20 Sebastian Peryt <sebastian.peryt@intel.com>
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* config.gcc: Support "knm".
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* config/i386/driver-i386.c (host_detect_local_cpu): Detect "knm".
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* config/i386/i386-c.c (ix86_target_macros_internal): Handle
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PROCESSOR_KNM.
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* config/i386/i386.c (m_KNM): Define.
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(processor_target_table): Add "knm".
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(PTA_KNM): Define.
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(ix86_option_override_internal): Add "knm".
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(ix86_issue_rate): Add PROCESSOR_KNM.
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(ix86_adjust_cost): Ditto.
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(ia32_multipass_dfa_lookahead): Ditto.
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(get_builtin_code_for_version): Handle PROCESSOR_KNM.
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(fold_builtin_cpu): Add M_INTEL_KNM.
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* config/i386/i386.h (processor_costs): Define TARGET_KNM.
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(processor_type): Add PROCESSOR_KNM.
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* config/i386/x86-tune.def: Add m_KNM.
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* doc/invoke.texi: Add knm as x86 -march=/-mtune= CPU type.
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2017-09-20 Richard Biener <rguenther@suse.de>
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PR tree-optimization/80213
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@ -97,7 +117,7 @@
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* rtl.h (get_stack_check_protect): Prototype.
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* target.def (stack_clash_protection_final_dynamic_probe): New hook.
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* targhooks.c (default_stack_clash_protection_final_dynamic_probe): New.
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* targhooks.h (default_stack_clash_protection_final_dynamic_probe):
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* targhooks.h (default_stack_clash_protection_final_dynamic_probe):
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Prototype.
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* doc/tm.texi.in (TARGET_STACK_CLASH_PROTECTION_FINAL_DYNAMIC_PROBE):
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Add @hook.
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@ -312,8 +332,8 @@
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2017-09-17 Daniel Santos <daniel.santos@pobox.com>
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config/i386/i386.c: (xlogue_layout::STUB_NAME_MAX_LEN): Increase to 20
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bytes.
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* config/i386/i386.c (xlogue_layout::STUB_NAME_MAX_LEN):
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Increase to 20 bytes.
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(xlogue_layout::s_stub_names): Add an additional size-2 diminsion.
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(xlogue_layout::get_stub_name): Modify to select the appropairate sse
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or avx version of the stub.
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@ -623,7 +623,7 @@ pentium4 pentium4m pentiumpro prescott lakemont"
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x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \
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bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
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core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
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sandybridge ivybridge haswell broadwell bonnell silvermont knl \
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sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \
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skylake-avx512 x86-64 native"
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# Additional x86 processors supported by --with-cpu=. Each processor
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@ -790,6 +790,10 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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/* Knights Landing. */
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cpu = "knl";
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break;
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case 0x85:
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/* Knights Mill. */
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cpu = "knm";
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break;
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default:
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if (arch)
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{
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@ -797,6 +801,9 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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/* Assume Knights Landing. */
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if (has_avx512f)
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cpu = "knl";
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/* Assume Knights Mill */
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else if (has_avx5124vnniw)
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cpu = "knm";
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/* Assume Skylake. */
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else if (has_clflushopt)
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cpu = "skylake";
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@ -176,6 +176,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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def_or_undef (parse_in, "__knl");
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def_or_undef (parse_in, "__knl__");
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break;
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case PROCESSOR_KNM:
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def_or_undef (parse_in, "__knm");
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def_or_undef (parse_in, "__knm__");
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break;
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case PROCESSOR_SKYLAKE_AVX512:
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def_or_undef (parse_in, "__skylake_avx512");
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def_or_undef (parse_in, "__skylake_avx512__");
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@ -292,6 +296,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
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case PROCESSOR_KNL:
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def_or_undef (parse_in, "__tune_knl__");
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break;
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case PROCESSOR_KNM:
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def_or_undef (parse_in, "__tune_knm__");
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break;
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case PROCESSOR_SKYLAKE_AVX512:
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def_or_undef (parse_in, "__tune_skylake_avx512__");
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break;
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@ -2192,6 +2192,7 @@ const struct processor_costs *ix86_cost = &pentium_cost;
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#define m_BONNELL (1U<<PROCESSOR_BONNELL)
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#define m_SILVERMONT (1U<<PROCESSOR_SILVERMONT)
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#define m_KNL (1U<<PROCESSOR_KNL)
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#define m_KNM (1U<<PROCESSOR_KNM)
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#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512)
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#define m_INTEL (1U<<PROCESSOR_INTEL)
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@ -2903,6 +2904,7 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
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{"bonnell", &atom_cost, 16, 15, 16, 7, 16},
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{"silvermont", &slm_cost, 16, 15, 16, 7, 16},
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{"knl", &slm_cost, 16, 15, 16, 7, 16},
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{"knm", &slm_cost, 16, 15, 16, 7, 16},
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{"skylake-avx512", &core_cost, 16, 10, 16, 10, 16},
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{"intel", &intel_cost, 16, 15, 16, 7, 16},
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{"geode", &geode_cost, 0, 0, 0, 0, 0},
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@ -5352,6 +5354,8 @@ ix86_option_override_internal (bool main_args_p,
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(PTA_CORE2 | PTA_MOVBE)
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#define PTA_SILVERMONT \
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(PTA_WESTMERE | PTA_MOVBE)
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#define PTA_KNM \
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(PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ)
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/* if this reaches 64, need to widen struct pta flags below */
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@ -5422,6 +5426,7 @@ ix86_option_override_internal (bool main_args_p,
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{"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
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{"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
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{"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
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{"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
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{"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
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{"geode", PROCESSOR_GEODE, CPU_GEODE,
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PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
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@ -30282,6 +30287,7 @@ ix86_issue_rate (void)
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case PROCESSOR_BONNELL:
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case PROCESSOR_SILVERMONT:
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case PROCESSOR_KNL:
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case PROCESSOR_KNM:
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case PROCESSOR_INTEL:
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case PROCESSOR_K6:
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case PROCESSOR_BTVER2:
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@ -30648,6 +30654,7 @@ ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
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case PROCESSOR_SILVERMONT:
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case PROCESSOR_KNL:
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case PROCESSOR_KNM:
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case PROCESSOR_INTEL:
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if (!reload_completed)
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return cost;
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@ -30719,6 +30726,7 @@ ia32_multipass_dfa_lookahead (void)
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case PROCESSOR_BONNELL:
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case PROCESSOR_SILVERMONT:
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case PROCESSOR_KNL:
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case PROCESSOR_KNM:
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case PROCESSOR_INTEL:
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/* Generally, we want haifa-sched:max_issue() to look ahead as far
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as many instructions can be executed on a cycle, i.e.,
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@ -33844,6 +33852,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
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arg_str = "knl";
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priority = P_PROC_AVX512F;
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break;
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case PROCESSOR_KNM:
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arg_str = "knm";
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priority = P_PROC_AVX512F;
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break;
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case PROCESSOR_SILVERMONT:
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arg_str = "silvermont";
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priority = P_PROC_SSE4_2;
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@ -34527,6 +34539,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
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M_AMD_BTVER1,
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M_AMD_BTVER2,
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M_AMDFAM17H,
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M_INTEL_KNM,
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M_CPU_SUBTYPE_START,
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M_INTEL_COREI7_NEHALEM,
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M_INTEL_COREI7_WESTMERE,
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@ -34570,6 +34583,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
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{"bonnell", M_INTEL_BONNELL},
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{"silvermont", M_INTEL_SILVERMONT},
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{"knl", M_INTEL_KNL},
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{"knm", M_INTEL_KNM},
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{"amdfam10h", M_AMDFAM10H},
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{"barcelona", M_AMDFAM10H_BARCELONA},
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{"shanghai", M_AMDFAM10H_SHANGHAI},
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@ -351,6 +351,7 @@ extern const struct processor_costs ix86_size_cost;
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#define TARGET_BONNELL (ix86_tune == PROCESSOR_BONNELL)
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#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
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#define TARGET_KNL (ix86_tune == PROCESSOR_KNL)
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#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
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#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
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#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
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#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
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@ -2250,6 +2251,7 @@ enum processor_type
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PROCESSOR_BONNELL,
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PROCESSOR_SILVERMONT,
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PROCESSOR_KNL,
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PROCESSOR_KNM,
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PROCESSOR_SKYLAKE_AVX512,
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PROCESSOR_INTEL,
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PROCESSOR_GEODE,
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@ -41,7 +41,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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/* X86_TUNE_SCHEDULE: Enable scheduling. */
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DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
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m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
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| m_INTEL | m_KNL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
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| m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
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on modern chips. Preffer stores affecting whole integer register
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@ -49,7 +49,7 @@ DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
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value over movb. */
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DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
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m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
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| m_KNL | m_AMD_MULTIPLE | m_GENERIC)
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| m_KNL | m_KNM | m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
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destinations to be 128bit to allow register renaming on 128bit SSE units,
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@ -85,13 +85,13 @@ DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
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partial dependencies. */
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DEF_TUNE (X86_TUNE_MOVX, "movx",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
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| m_KNL | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GENERIC)
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| m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
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full sized loads. */
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DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
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m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
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| m_KNL | m_AMD_MULTIPLE | m_GENERIC)
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| m_KNL | m_KNM | m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
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conditional jump instruction for 32 bit TARGET.
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@ -125,7 +125,7 @@ DEF_TUNE (X86_TUNE_REASSOC_INT_TO_PARALLEL, "reassoc_int_to_parallel",
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/* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
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during reassociation of fp computation. */
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DEF_TUNE (X86_TUNE_REASSOC_FP_TO_PARALLEL, "reassoc_fp_to_parallel",
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m_BONNELL | m_SILVERMONT | m_HASWELL | m_KNL |m_INTEL | m_BDVER1
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m_BONNELL | m_SILVERMONT | m_HASWELL | m_KNL | m_KNM |m_INTEL | m_BDVER1
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| m_BDVER2 | m_ZNVER1 | m_GENERIC)
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/*****************************************************************************/
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@ -145,7 +145,7 @@ DEF_TUNE (X86_TUNE_REASSOC_FP_TO_PARALLEL, "reassoc_fp_to_parallel",
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regression on mgrid due to IRA limitation leading to unecessary
|
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use of the frame pointer in 32bit mode. */
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DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
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m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL
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m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
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| m_ATHLON_K8)
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/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
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|
@ -207,8 +207,8 @@ DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
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/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
|
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than 4 branch instructions in the 16 byte window. */
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DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
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m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL |m_INTEL |
|
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m_ATHLON_K8 | m_AMDFAM10)
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m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM
|
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|m_INTEL | m_ATHLON_K8 | m_AMDFAM10)
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|
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/*****************************************************************************/
|
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/* Integer instruction selection tuning */
|
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|
|
@ -231,22 +231,22 @@ DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO))
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/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions. */
|
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DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
|
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~(m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
|
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| m_KNL | m_GENERIC))
|
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| m_KNL | m_KNM | m_GENERIC))
|
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|
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/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
|
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for DFmode copies */
|
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DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
|
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~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
|
||||
| m_KNL | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GENERIC))
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| m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GENERIC))
|
||||
|
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/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
|
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will impact LEA instruction selection. */
|
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DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
|
||||
| m_INTEL)
|
||||
| m_KNM | m_INTEL)
|
||||
|
||||
/* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation. */
|
||||
DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr",
|
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m_BONNELL | m_SILVERMONT | m_KNL)
|
||||
m_BONNELL | m_SILVERMONT | m_KNL | m_KNM)
|
||||
|
||||
/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
|
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vector path on AMD machines.
|
||||
|
|
@ -263,7 +263,7 @@ DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
|
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/* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
|
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a conditional move. */
|
||||
DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
|
||||
m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL)
|
||||
m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL)
|
||||
|
||||
/* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
|
||||
as MOVS and STOS (without a REP prefix) to move/set sequences of bytes. */
|
||||
|
|
@ -281,17 +281,17 @@ DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
|
|||
/* X86_TUNE_USE_SAHF: Controls use of SAHF. */
|
||||
DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
|
||||
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
|
||||
| m_KNL | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
|
||||
| m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
|
||||
| m_BTVER | m_ZNVER1 | m_GENERIC)
|
||||
|
||||
/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
|
||||
DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
|
||||
~(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL
|
||||
~(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
|
||||
| m_K6))
|
||||
|
||||
/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
|
||||
DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
|
||||
m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL
|
||||
m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
|
||||
| m_LAKEMONT | m_AMD_MULTIPLE | m_GENERIC)
|
||||
|
||||
/*****************************************************************************/
|
||||
|
|
@ -308,7 +308,7 @@ DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
|
|||
integer operand. */
|
||||
DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
|
||||
~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
|
||||
| m_SILVERMONT | m_KNL | m_INTEL | m_AMD_MULTIPLE | m_GENERIC))
|
||||
| m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE | m_GENERIC))
|
||||
|
||||
/* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
|
||||
DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
|
||||
|
|
@ -316,7 +316,7 @@ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
|
|||
/* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI. */
|
||||
DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
|
||||
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
|
||||
| m_KNL | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GENERIC)
|
||||
| m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GENERIC)
|
||||
|
||||
/*****************************************************************************/
|
||||
/* SSE instruction selection tuning */
|
||||
|
|
@ -330,13 +330,13 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
|
|||
/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
|
||||
of a sequence loading registers by parts. */
|
||||
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
|
||||
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL
|
||||
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM
|
||||
| m_INTEL | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER1 | m_GENERIC)
|
||||
|
||||
/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead
|
||||
of a sequence loading registers by parts. */
|
||||
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
|
||||
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL
|
||||
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM
|
||||
| m_INTEL | m_BDVER | m_ZNVER1 | m_GENERIC)
|
||||
|
||||
/* Use packed single precision instructions where posisble. I.e. movups instead
|
||||
|
|
@ -375,7 +375,7 @@ DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
|
|||
/* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for
|
||||
fp converts to destination register. */
|
||||
DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
|
||||
m_SILVERMONT | m_KNL | m_INTEL)
|
||||
m_SILVERMONT | m_KNL | m_KNM | m_INTEL)
|
||||
|
||||
/* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
|
||||
from FP to FP. This form of instructions avoids partial write to the
|
||||
|
|
@ -389,7 +389,7 @@ DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
|
|||
|
||||
/* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction. */
|
||||
DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
|
||||
m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL)
|
||||
m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL)
|
||||
|
||||
/* X86_TUNE_VECTOR_PARALLEL_EXECUTION: Indicates tunings with ability to
|
||||
execute 2 or more vector instructions in parallel. */
|
||||
|
|
@ -550,4 +550,4 @@ DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4)
|
|||
/* X86_TUNE_ONE_IF_CONV_INSNS: Restrict a number of cmov insns in
|
||||
if-converted sequence to one. */
|
||||
DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
|
||||
m_SILVERMONT | m_KNL | m_INTEL | m_CORE_ALL | m_GENERIC)
|
||||
m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GENERIC)
|
||||
|
|
|
|||
|
|
@ -25089,6 +25089,12 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
|
|||
BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER and
|
||||
AVX512CD instruction set support.
|
||||
|
||||
@item knm
|
||||
Intel Knights Mill CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
|
||||
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
|
||||
BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER, AVX512CD,
|
||||
AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
|
||||
|
||||
@item skylake-avx512
|
||||
Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
|
||||
SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2017-09-20 Sebastian Peryt <sebastian.peryt@intel.com>
|
||||
|
||||
* gcc.target/i386/builtin_target.c: Test knm.
|
||||
* gcc.target/i386/funcspec-56.inc: Test arch=knm.
|
||||
|
||||
2017-09-20 Richard Biener <rguenther@suse.de>
|
||||
|
||||
PR tree-optimization/77362
|
||||
|
|
|
|||
|
|
@ -42,6 +42,10 @@ check_intel_cpu_model (unsigned int family, unsigned int model,
|
|||
/* Knights Landing. */
|
||||
assert (__builtin_cpu_is ("knl"));
|
||||
break;
|
||||
case 0x85:
|
||||
/* Knights Mill */
|
||||
assert (__builtin_cpu_is ("knm"));
|
||||
break;
|
||||
case 0x1a:
|
||||
case 0x1e:
|
||||
case 0x1f:
|
||||
|
|
|
|||
|
|
@ -142,6 +142,7 @@ extern void test_arch_corei7 (void) __attribute__((__target__("arch=corei7")));
|
|||
extern void test_arch_corei7_avx (void) __attribute__((__target__("arch=corei7-avx")));
|
||||
extern void test_arch_core_avx2 (void) __attribute__((__target__("arch=core-avx2")));
|
||||
extern void test_arch_knl (void) __attribute__((__target__("arch=knl")));
|
||||
extern void test_arch_knm (void) __attribute__((__target__("arch=knm")));
|
||||
extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512")));
|
||||
extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
|
||||
extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));
|
||||
|
|
|
|||
|
|
@ -1,30 +1,35 @@
|
|||
2017-09-20 Sebastian Peryt <sebastian.peryt@intel.com>
|
||||
|
||||
* config/i386/cpuinfo.h (processor_types): Add INTEL_KNM.
|
||||
* config/i386/cpuinfo.c (get_intel_cpu): Detect Knights Mill.
|
||||
|
||||
2017-09-17 Daniel Santos <daniel.santos@pobox.com>
|
||||
|
||||
config/i386/i386-asm.h (PASTE2): New macro.
|
||||
* config/i386/i386-asm.h (PASTE2): New macro.
|
||||
(ASMNAME): Modify to use PASTE2.
|
||||
(MS2SYSV_STUB_PREFIX): New macro for isa prefix.
|
||||
(MS2SYSV_STUB_BEGIN, MS2SYSV_STUB_END): New macros for stub headers.
|
||||
config/i386/resms64.S: Rename to a header file, use MS2SYSV_STUB_BEGIN
|
||||
* config/i386/resms64.S: Rename to a header file, use MS2SYSV_STUB_BEGIN
|
||||
instead of HIDDEN_FUNC and MS2SYSV_STUB_END instead of FUNC_END.
|
||||
config/i386/resms64f.S: Likewise.
|
||||
config/i386/resms64fx.S: Likewise.
|
||||
config/i386/resms64x.S: Likewise.
|
||||
config/i386/savms64.S: Likewise.
|
||||
config/i386/savms64f.S: Likewise.
|
||||
config/i386/avx_resms64.S: New file that only defines a macro and
|
||||
* config/i386/resms64f.S: Likewise.
|
||||
* config/i386/resms64fx.S: Likewise.
|
||||
* config/i386/resms64x.S: Likewise.
|
||||
* config/i386/savms64.S: Likewise.
|
||||
* config/i386/savms64f.S: Likewise.
|
||||
* config/i386/avx_resms64.S: New file that only defines a macro and
|
||||
includes it's corresponding header file.
|
||||
config/i386/avx_resms64f.S: Likewise.
|
||||
config/i386/avx_resms64fx.S: Likewise.
|
||||
config/i386/avx_resms64x.S: Likewise.
|
||||
config/i386/avx_savms64.S: Likewise.
|
||||
config/i386/avx_savms64f.S: Likewise.
|
||||
config/i386/sse_resms64.S: Likewise.
|
||||
config/i386/sse_resms64f.S: Likewise.
|
||||
config/i386/sse_resms64fx.S: Likewise.
|
||||
config/i386/sse_resms64x.S: Likewise.
|
||||
config/i386/sse_savms64.S: Likewise.
|
||||
config/i386/sse_savms64f.S: Likewise.
|
||||
config/i386/t-msabi: Modified to add avx and sse versions of stubs.
|
||||
* config/i386/avx_resms64f.S: Likewise.
|
||||
* config/i386/avx_resms64fx.S: Likewise.
|
||||
* config/i386/avx_resms64x.S: Likewise.
|
||||
* config/i386/avx_savms64.S: Likewise.
|
||||
* config/i386/avx_savms64f.S: Likewise.
|
||||
* config/i386/sse_resms64.S: Likewise.
|
||||
* config/i386/sse_resms64f.S: Likewise.
|
||||
* config/i386/sse_resms64fx.S: Likewise.
|
||||
* config/i386/sse_resms64x.S: Likewise.
|
||||
* config/i386/sse_savms64.S: Likewise.
|
||||
* config/i386/sse_savms64f.S: Likewise.
|
||||
* config/i386/t-msabi: Modified to add avx and sse versions of stubs.
|
||||
|
||||
2017-09-01 Olivier Hainque <hainque@adacore.com>
|
||||
|
||||
|
|
|
|||
|
|
@ -137,6 +137,10 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
|
|||
/* Knights Landing. */
|
||||
__cpu_model.__cpu_type = INTEL_KNL;
|
||||
break;
|
||||
case 0x85:
|
||||
/* Knights Mill. */
|
||||
__cpu_model.__cpu_type = INTEL_KNM;
|
||||
break;
|
||||
case 0x1a:
|
||||
case 0x1e:
|
||||
case 0x1f:
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ enum processor_types
|
|||
AMD_BTVER1,
|
||||
AMD_BTVER2,
|
||||
AMDFAM17H,
|
||||
INTEL_KNM,
|
||||
CPU_TYPE_MAX
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue