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Merge from rewrite branch.

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From-SVN: r66318
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Eric Christopher 2003-05-01 02:33:13 +00:00
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15 changed files with 13754 additions and 8328 deletions
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2003-04-30 Eric Christopher <echristo@redhat.com>
Richard Sandiford <rsandifo@redhat.com>
* configure: Regenerate from patches below.
* combine.c (gen_lowpart_for_combine): Fix comment and add tests
for all symbolic operands.
* config/mips/mips.c: Migrate RTX_COSTS and CONST_COSTS
to function.
* config/mips/linux.h: Fix typo.
* Merge from mips-3_4-rewrite branch:
2003-04-07 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (mips_classify_symbol): Add catch-all case for
handling local labels when TARGET_ABICALLS.
2003-04-04 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (mips_expand_epilogue): Add an
integer argument.
(mips_expand_call): Likewise.
* config/mips/mips.h (TARGET_SIBCALLS): New macro.
(FIXED_REGISTERS): Clear $31 entry.
(CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTER): Likewise.
(EPILOGUE_USES): Define.
* config/mips/mips.c (mips_function_ok_for_sibcall): New function.
(TARGET_FUNCTION_OK_FOR_SIBCALL): Use it.
(override_options): Add a 'j' register class.
(mips_expand_call): Handle sibcalls
(mips_expand_epilogue): Handle epilogues for sibcalls.
* config/mips/mips.md (epilogue): Adjust call to mips_expand_epilogue.
(sibcall_epilogue): New pattern.
(call, call_value): Adjust calls to mips_expand_call.
(sibcall, sibcall_value): New expanders.
(sibcall_internal, sibcall_value_internal): New patterns.
(sibcall_value_multiple_internal): New pattern.
2003-03-25 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (extended_mips16): New attribute.
(define_attr length): Default to 8 if extended_mips16 == yes.
(truncdisi2): Set extended_mips16 to yes for the sll alternative.
(truncdihi2, truncdiqi2, *extendsidi2): Likewise.
(call_internal): Set extended_mips16 to yes for direct jumps.
Remove redundant mode attribute.
(call_value_internal, call_value_multiple_internal): Likewise.
(call_split): Remove redundant mode attribute.
(call_value_split, call_value_multiple_split): Likewise.
* config/mips/mips.c (mips_symbol_insns): Rework. Fix handling
of unaligned offsets.
* config/mips/mips.c (mips_splittable_symbol_p): Fix handling
of SYMBOL_GENERAL.
2003-03-22 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (TARGET_EXPLICIT_RELOCS): Add commentary.
* config/mips/mips.c (override_options): Disable -mexplicit-relocs
for mips16 code.
2003-03-22 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (ADDRESS_COST): Define.
2003-03-20 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (EXTRA_CONSTRAINT): Give existing meaning of
'R' to 'U'. Make 'R' mean a single-instruction memory reference.
* config/mips/mips.md: Replace 'R' constraints with 'U'.
2003-03-18 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (truncdisi2): Add commentary. Use sll instead
of a two-instruction sequence. Add register->memory alternative.
(truncdihi2, truncdiqi2): Likewise.
Rework shift/truncate instructions so that they only handle right
shifts of 32 (or more, in the case of arithmetic shifts).
Add patterns for truncate/sign-extend.
2003-03-13 Richard Sandiford <rsandifo@redhat.com>
* configure.in (mips*-*-*): Check for explicit relocation support.
* configure: Regenerate.
2003-03-13 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (TARGET_SWITCHES): Add -mexplicit-relocs
and -mno-explicit-relocs.
(MASK_EXPLICIT_RELOCS): Define.
(TARGET_EXPLICIT_RELOCS): Use it.
(mips_split_addresses): Remove declaration.
* config/mips/mips.c (override_options): Update comment for
mips_split_addresses. Clear MASK_EXPLICIT_RELOCS for non-PIC n64.
2003-03-13 Richard Sandiford <rsandifo@redhat.com>
* combine.c (gen_lowpart_for_combine): Treat the lowpart Pmode of
a CONST as identity. Check the return value of gen_lowpart_common.
2003-03-13 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (mips_legitimize_symbol): Handle small data
references for TARGET_EXPLICIT_RELOCS.
(mips_reloc_string): Return "%gp_rel(" for RELOC_GPREL16 if
!TARGET_MIPS16.
2003-03-13 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md: Replace 'IQ' mips16 constraints with just 'Q'.
(addsi3): Remove redundant constraints.
(addsi3_internal): Use separate register & constant alternatives.
Use a 'Q' constraint and "addiu" insn for the latter.
(adddi3_internal_3, addsi3_internal_2): Likewise.
2003-03-13 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (mips_expand_unaligned_load): Declare.
(mips_expand_unaligned_store): Declare.
* config/mips/mips.c (mips_get_unaligned_mem): New fn.
(mips_expand_unaligned_load, mips_expand_unaligned_store): New fns.
* config/mips/mips.md (UNSPEC_ULW, UNSPEC_USW): Remove.
(UNSPEC_ULD, UNSPEC_USD): Remove.
(UNSPEC_LWL, UNSPEC_LWR, UNSPEC_SWL, UNSPEC_SWR): New.
(UNSPEC_LDL, UNSPEC_LDR, UNSPEC_SDL, UNSPEC_SDR): New.
(extv, extzv): Use mips_expand_unaligned_load.
(insv): Use mips_expand_unaligned_store. Use a reg_or_0_operand
predicate for operand 3.
(movsi_ulw, movsi_usw): Replace with...
(mov_lwl, mov_lwr, mov_swl, move_swr): ...these new insns.
(movdi_uld, movdi_usd): Likewise replace with...
(mov_ldl, mov_ldr, mov_sdl, move_sdr): ...these insns.
2003-02-26 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (mips_global_pic_constant_p): Declare.
* config/mips/mips.h (LEA_REGS): New register class.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add entries for it.
(GR_REG_CLASS_P): Include LEA_REGS.
(DANGEROUS_FOR_LA25_P): New macro.
(EXTRA_CONSTRAINT): Add !DANGEROUS_FOR_LA25_P to R's condition.
Add a T constraint for the DANGEROUS_FOR_LA25_P case.
* config/mips/mips.c (mips_regno_to_class): Change GR_REGS
entries to LEA_REGS.
(mips_global_pic_constant_p): New function.
(override_options): Add 'e' register constraint.
(mips_secondary_reload_class): Return LEA_REGS when reloading
a dangerous constant into a class containing $25.
* config/mips/mips.md (movdi_internal2): Add an e <- T alternative.
(movsi_internal): Likewise.
2003-02-23 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (TARGET_SPLIT_CALLS): New macro.
* config/mips/mips.md (call_split): New insn.
(call_value_split, call_value_multiple_split): New insns.
(call_internal): Turn into a define_insn_and_split. Split the
instruction into a call and $gp load if TARGET_SPLIT_CALLS.
(call_value_internal, call_value_multiple_internal): Likewise.
2003-02-23 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (mips_reloc_string): Return "%got(" for
RELOC_GOT_PAGE and RELOC_GOT_DISP if !TARGET_NEWABI.
(mips_encode_section_info): Don't take symbol visibility into
account if TARGET_ABICALLS. Add more commentary.
* config/mips/mips.md: Add commentary above reloc constants.
2003-02-12 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (mips_legitimize_const_move): New, extracted
from mips_legitimize_move. Legitimize constant pool references.
(mips_legitimize_move): Call mips_legitimize_const_move. Attach
a REG_EQUAL note to the last instruction.
2003-02-11 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (mips_simplify_dwarf_addr): Declare.
* config/mips/mips.h (TARGET_EXPLICIT_RELOCS, TARGET_NEWABI): New.
(ASM_SIMPLIFY_DWARF_ADDR): Define to mips_simplify_dwarf_addr.
(EXTRA_CONSTRAINT): Allow symbolic call addresses for TARGET_ABICALLS.
* config/mips/mips.md (UNSPEC_HIGH): New constant.
(UNSPEC_RELOC_GPREL16): Rename to...
(RELOC_GPREL16): ...this.
(RELOC_GOT_HI, RELOC_GOT_LO, RELOC_GOT_PAGE, RELOC_GOT_DISP): New.
(RELOC_CALL16, RELOC_CALL_HI, RELOC_CALL_LO): New.
(macro_calls): New attribute.
(length): Use it to set the default length of calls. Don't allow
calls to have delay slots if macro_calls is "yes".
(luisi, luidi): New patterns.
(lowsi, lowdi): Use '%R' to print the relocation.
(lowdi_extend): Remove.
(loadgp): Remove mode from operand 0. Use '%0' instead of '%a0'.
(call_internal): Merge alternatives. Always use "jal".
(call_value_internal, call_value_multiple_internal): Likewise.
(reloc_gprel16): Remove.
* config/mips/mips.c (mips_got_alias_set): New variable.
(mips_classify_constant): Handle the new relocation constants.
(mips_classify_symbol): Reverse the sense of SYMBOL_REF_FLAG for PIC.
(mips_symbolic_address_p): Return false if generating explicit relocs.
Otherwise allow local PIC symbols to have an offset.
(mips_splittable_symbol_p): New function.
(mips_classify_address): Use it to check whether a LO_SUM is valid.
(mips_const_insns): Always accept HIGH.
(call_insn_operand): Don't accept global symbols if using explicit
relocs.
(move_operand): Don't accept HIGH when generating PIC.
(mips_reloc, mips_lui_reloc): New functions.
(mips_force_temporary): Remove MODE argument. Expect VALUE to
be a valid right-hand-side for a SET pattern.
(mips_load_got, mips_load_got16, mips_load_got32): New functions.
(mips_emit_high): New function.
(mips_legitimize_symbol): Use mips_reloc for the mips16 gp-relative
case. Use mips_splittable_symbol_p to check whether a LO_SUM
address should be used. Use mips_emit_high to generate the
high part of such an address. Adjust the global symbol + offset
case to match the change to mips_force_temprorary.
(mips_legitimize_move): Shuffle call to mips_legitimize_symbol.
If generating explicit-reloc PIC, load the address of global
symbols from the GOT. Use mips_emit_high to emit the high part
of an address.
(mips_simplify_dwarf_addr): New function.
(mips_move_1word): Use lwc1 instead of l.s and swc1 instead of s.s.
(mips_move_2words): Likewise ldc1/l.d and sdc1/s.d if TARGET_64BIT.
(mips_expand_call): Load the addresses of global functions using
%call* relocs if generating explicit-reloc PIC. Don't generate
an exception_receiver pattern.
(override_options): Initialize mips_got_alias_set.
(print_relocation): Remove in favour of...
(mips_reloc_string): ...this new function.
(print_operand): Handle '%R'. Use mips_reloc_string.
(print_operand_address): Use print_operand to print the symbolic
part of a LO_SUM address.
(mips_output_function_prologue): Use .cprestore, reverting last patch.
(mips_encode_section_info): Factor out DECL_RTL accesses. Reverse
sense of SYMBOL_REF_FLAG for PIC, using binds_local_p to check
for local symbols.
2003-02-02 Eric Christopher <echristo@redhat.com>
* config/mips/mips.c (mips_sign_extend): Remove.
* config/mips/mips-protos.h: Ditto.
* config/mips/mips.md (movdi_internal2_extend): Remove.
(extendsidi2): Fix mode of convert_memory_address.
2003-01-24 Eric Christopher <echristo@redhat.com>
* config/mips/mips.md: Rewrite zero_extend* and extend*
patterns. Use explicit instructions and split after reload
for register extensions.
(ashlsi3_internal1_extend): New combiner pattern for
shift and extend combinations.
* config/mips/mips.h: Change Pmode back to ptr_mode
for performance enhancement.
* combine.c (expand_compound_operation): Make sure
that zero_extend operation is profitable.
2003-01-14 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (TRAMPOLINE_TEMPLATE): Make size of stored
addresses depend on ptr_mode rather than Pmode.
(TRAMPOLINE_SIZE, TRAMPOLINE_ALIGNMENT): Update acoordingly.
(INITIALIZE_TRAMPOLINE): Rework to handle Pmode != ptr_mode.
(CASE_VECTOR_MODE): Use ptr_mode for !TARGET_MIPS16.
(ASM_OUTPUT_ADDR_VEC_ELT): Update accordingly.
* config/mips/mips.md (tablejump): Likewise. Remove Pmode
condition for selecting cpaddsi or cpadddi: use cpadd instead.
(tablejump_internal1): Remove condition.
(tablejump_internal2): Change condition to TARGET_64BIT.
(cpaddsi): Rename to...
(cpadd): ...this.
(cpadddi): Remove.
2003-01-09 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (mips16_constant_after_function_p,
mips_address_cost, mips_check_split, double_memory_operand,
mips16_gp_offset, mips16_gp_offset_p, mips16_constant,
pic_address_needs_scratch, symbolic_operand): Remove declarations.
(mips_legitimate_address_p): Return bool.
(mips_address_insns, mips_fetch_insns, mips_const_insns,
mips_legitimize_address, mips_legitimize_move,
mips_expand_call): Declare.
(mips_return_addr): Move outside #ifdef RTX_CODE.
* config/mips/mips.h (ABI_HAS_64BIT_SYMBOLS): New macro.
(PIC_FN_ADDR_REG): New reg_class.
(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add corresponding entries.
(GR_REG_CLASS_P): True for PIC_FN_ADDR_REG.
(SMALL_OPERAND, SMALL_OPERAND_UNSIGNED, LUI_OPERAND,
CONST_HIGH_PART, CONST_LOW_PART, LUI_INT): New macros.
(SMALL_INT, SMALL_INT_UNSIGNED, CONST_OK_FOR_LETTER_P): Use new macros.
(EXTRA_CONSTRAINTS): Give new meanings to Q, R and S.
(CONSTANT_ADDRESS_P): Use mips_legitimate_address_p.
(LEGITIMATE_PIC_OPERAND): Undefine.
(LEGITIMATE_CONSTANT_P): Use mips_const_insns.
(LEGITIMIZE_ADDRESS): Use mips_legitimize_address.
(CONSTANT_AFTER_FUNCTION_P): Remove definition in #if 0 block.
(FUNCTION_MODE): Change to SImode.
(CONST_COSTS): Use mips_const_insns to calculate the cost of
most constants. Treat const_artih_operands specially if they
occur in a PLUS or MINUS.
(CONSTANT_POOL_COST): New macro.
(RTX_COSTS): Use mips_address_insns for MEMs, with a base cost of 2.
Add LO_SUM handling.
(ADDRESS_COST): Undefine.
(PREDICATE_CODES): Add symbolic_operand and const_arith_operand.
Add CONST to the list of codes for arith_operand. Add LABEL_REF
to call_insn_operand and remove CONST_INT.
* config/mips/mips.c: Include integrate.h.
(SINGLE_WORD_MODE_P): New macro.
(mips_constant_type, mips_symbol_type, mips_address_type): New enums.
(mips_constant_info, mips_address_info): New structs.
(mips_regno_to_class): Map $25 to PIC_FN_ADDR_REG.
(mips_classify_constant, mips_classify_symbol,
mips_valid_base_register_p, mips_symbolic_address_p,
mips_classify_address, mips_symbol_insns,
mips16_unextended_reference_p, mips_address_insns, mips_const_insns,
mips_fetch_insns, mips_force_temporary, mips_add_offset,
mips_legitimize_symbol, mips_legitimize_address, mips_legitimize_move,
mips_print_relocation): New functions.
(const_arith_operand): New operand predicate.
(arith_operand): Use it.
(mips_const_double_ok, mips16_simple_memory_operand,
simple_memory_operand, double_memory_operand, mips_check_split,
mips_address_cost, pic_address_needs_scratch, mips16_gp_offset,
mips16_gp_offset_p, mips16_output_gp_offset,
mips16_constant_after_function_p, mips16_constant): Remove.
(call_insn_operand): Be more fussy about symbolic constants.
Use register_operand.
(move_operand): Use mips_symbolic_address_p to check symbolic
operands and general_operand to check the rest.
(symbolic_operand): Use mips_classify_constant.
(mips_legitimate_address_p): Use mips_classify_address.
(mips_move_1word): Combine handling of symbolic addresses.
Remove special treatment of gp-relative loads for TARGET_MIPS16.
(move_move_2words): Likewise. Assume addresses are offsettable
if they need to refer to more than one word. Add HIGH handling.
(mips_restore_gp): Use ptr_mode for the GP save slot.
(mips_expand_call): New function, combining the old mips.md
call and call_internal define_expands. If the address isn't
a call_insn_operand, force it into a register. For SVR4 PIC,
emit an exception_receiver instruction after the call.
(override_options): Only override flag_pic for TARGET_ABICALLS
if it is currently zero. Allow mips_split_addresses when
Pmode == DImode too, except when ABI_HAS_64BIT_SYMBOLS.
Add new register class letter, 'c'.
(print_operand): Use mips_classify_constant for constant operands.
(print_operand_address): Use mips_classify_address.
(mips_output_function_prologue): Don't use .cprestore.
(mips_expand_epilogue): For TARGET_MIPS16, only adjust the stack
via the frame pointer if current_function_calls_eh_return.
(mips_encode_section_info): For TARGET_ABICALLS, use SYMBOL_REF_FLAG
to mark whether a symbol is local or global.
(build_mips16_call_stub): Expect the address of the function rather
than a MEM reference to it. Update call generation sequences.
(mips16_optimize_gp): Remove Pmode checks. Temporarily disable
small-data adjustments.
* config/mips/mips.md: Remove 'R'/'m' memory distinction. Use default
length for loads and stores.
(UNSPEC_CPADD, UNSPEC_RELOC_GPREL16): New constants.
(define_attr type): Add const and prefetch.
(define_attr length): Use mips_const_insns for const instructions.
Use mips_fetch_insns for load and store instructions.
(define_attr single_insn): New.
(define_attr can_delay): Use it.
(define_attr abicalls): Remove.
(define_delay): Use can_delay. Always allow calls to have delay slots.
(addsi3_internal_2): Add 'Q' constraint.
(movsi_ulw, movsi_usw, movdi_uld, movdi_usd): Set length to 8.
(high): Remove.
(lowsi): Renamed from low.
(lowdi): New pattern.
(movdi, movsi): Use mips_legitimize_move. Remove define_split.
(lwxc1, ldxc1, swxc1, sdxc1): Set length to 4.
(loadgp): Change operand 0 to an immediate_operand.
(tablejump): Use the same patterns for SVR4 PIC but emit a cpadd
beforehand.
(cpaddsi, cpadddi): New patterns.
(tablejump_internal3, tablejump_internal4): Remove define_expands
and associated define_splits.
(call, call_value): Use mips_expand_call.
(call_internal): New, replacing all existing call_internal* insns.
(call_value_internal): Likewise call_value_internal*.
(call_value_multiple_internal): Likewise call_value_multiple_internal*.
(untyped_call): Remove if (operands[0]) magic.
(prefetch_si_address, prefetch_si): Change type to "prefetch".
(prefetch_di_address, prefetch_di): Likewise.
(leasi, leadi): Remove.
(reloc_gprel16): New.
* config/mips/5400.md (ir_vr54_hilo): Include const type.
* config/mips/5500.md (ir_vr55_hilo): Likewise.
* config/mips/sr71k.md (ir_sr70_hilo): Likewise.
2003-01-08 Eric Christopher <echristo@redhat.com>
* config.gcc (mipsisa32*): Change ABI_MEABI to ABI_EABI.
* config/mips/elf.h (STARTFILE_SPEC): Remove ABI_MEABI references and
configure check for libgloss.
* config/mips/elf64.h: Ditto.
* config/mips/mips.c: Remove ABI_MEABI.
* config/mips/mips.h: Ditto.
2002-11-05 Richard Sandiford <rsandifo@redhat.com>
Fix merge fallout.
* config/mips/mips.md (mul_acc_si): Reapply 2002-10-16 change.
(muldi3_internal): Remove outdated comment.
(*muls_di, *umuls_di): Fix comment and 64-bitness.
(*smsac_di, *umsac_di): Likewise. Reformat.
(umulsi3_highpart): Minor formatting tweaks.
(umulsi3_highpart_internal): Use only if !ISA_HAS_MULHI. Remove
redundant scratch operand. Minor formatting tweak.
(umulsi3_highpart_mulhi_internal): Use for !TARGET_64BIT as well.
(umulsi3_highpart_neg_mulhi_internal): Likewise. Fix asm template.
(smulsi3_highpart): As for the unsigned version.
(smulsi3_highpart_internal): Likewise.
(smulsi3_highpart_mulhi_internal): Likewise.
(smulsi3_highpart_neg_mulhi_internal): Likewise.
(smuldi3_highpart, umuldi3_highpart): Minor formatting tweaks.
(*smul_acc_di): Remove duplicated pattern.
(*umul_acc_di, *smul_acc_di): Reapply 2002-10-16 change.
(anddi3) [unnamed mips16 pattern]: Remove reintroduced length.
(zero_extendsidi2_internal2): Remove new, but commented-out pattern.
2002-10-22 Eric Christopher <echristo@redhat.com>
* config/mips/mips-protos.h (mips_return_addr): New.
* config/mips/mips.c (mips_return_addr): New.
(movdi_operand): Remove.
(se_register_operand): Ditto.
(se_reg_or_0_operand): Ditto.
(se_uns_arith_operand): Ditto.
(se_arith_operand): Ditto.
(se_nonmemory_operand): Ditto.
(extend_operator): Ditto.
(highpart_shift_operator): Ditto.
(mips_initial_elimination_offset): Remove return address pointer
elimination.
(mips_reg_names): Remove $ra.
(mips_regno_to_class): Ditto.
* config/mips/mips.h (POINTER_SIZE): Define based on TARGET_LONG64
and TARGET_64BIT.
(POINTER_BOUNDARY): Remove.
(POINTERS_EXTEND_UNSIGNED): Define to 0.
(PROMOTE_MODE): Promote to Pmode.
(SHORT_IMMEDIATES_SIGN_EXTEND): Define.
(Pmode): Define to TARGET_64BIT.
(FUNCTION_MODE): Define as Pmode.
(mips_args): Remove deleted functions.
(SIZE_TYPE): Depend on POINTER_SIZE.
(PTRDIFF_TYPE): Ditto.
(FIXED_REGISTERS): Fix extra registers.
(CALL_USED_REGISTERS): Ditto.
(CALL_REALLY_USED_REGISTERS): Ditto.
(RAP_REG_NUM): Remove.
(RETURN_ADDRESS_POINTER_REGNUM): Ditto.
(RETURN_ADDR_RTX): Define to mips_return_addr.
(ELIMINABLE_REGS): Remove RETURN_ADDRESS_POINTER_REGNUM.
(CAN_ELIMINATE): Ditto.
* config/mips/mips.md: For DImode patterns, take into account
deletions above. Split mulsidi patterns into sign_extend and
zero_extend.
2002-10-16 Richard Sandiford <rsandifo@redhat.com>
Michael Meissner <meissner@redhat.com>
* config/mips/mips.h (ISA_HAS_MACC): True for normal-mode vr4120 code.
* config/mips/mips.md (mulsi3_mult3): Add a define_peephole2 to
mop up unnecessarly moves through LO.
(*mul_acc_si): Remove vr5400 and vr5500 handling from here.
(*macc): New pattern for ISA_HAS_MACC. Add define_peephole2s to
change mtlo/macc sequences into mul/add sequences when a three-
address mul is available.
(*macc2): New pattern. Add a define_peephole2 to generate it.
(*mul_sub_si): Fix contraint for operand 5.
(*muls): Use in 32-bit code as well.
(*msac): Likewise. Use msub instead of msac in vr5500 code
if the destination is LO. Remove duplicate define_split.
(*muls_di): Use only in 32-bit code. Adjust rtl accordingly.
(*msac_di): Likewise. Fix formatting.
(smulsi3_highpart, umulsi3_highpart): Use mulhi in 32-bit code too.
(*xmulsi3_highpart_internal): Use only if !ISA_HAS_MULHI.
(*xmulsi3_highpart_mulhi): Use even if !TARGET_64BIT.
(*xmulsi3_neg_highpart_mulhi): Likewise.
(*mul_acc_64bit_di): Remove.
(*mul_acc_di): Use only in 32-bit code. Handle ISA_HAS_MACC as well.
2002-10-14 Richard Sandiford <rsandifo@redhat.com>
* config/mips/vr.h (DRIVER_SELF_SPECS): Define.
* config/mips/t-vr (MULTILIB_OPTIONS): Remove mlong32.
(MULTILIB_DIRNAMES): Remove long32.
(MULTILIB_EXCEPTIONS): Don't build -mabi=32 -mgp32 multilibs.
(MULTILIB_REDUNDANT_DIRS): Remove.
2002-10-14 Richard Sandiford <rsandifo@redhat.com>
* doc/tm.texi (DRIVER_SELF_SPECS): Document.
* gcc.c (driver_self_specs): New variable.
(do_self_spec): New function.
(main): Use it to process driver_self_specs.
2002-10-09 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (one_cmpldi2): Use only if TARGET_64BIT.
Remove DImode define_split for !TARGET_64BIT.
(anddi3): Remove !TARGET_64BIT support from here as well.
Change operand 2's predicate to se_uns_arith_operand.
Add constant alternatives to define_insn.
(iordi3, xordi3, *nordi3): Likewise.
(anddi3_internal1, xordi3_immed): Remove.
2002-10-01 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.h (PROCESSOR_R4121): Rename to PROCESSOR_R4120.
(TARGET_MIPS4121): Rename to TARGET_MIPS4120.
* config/mips/mips.c (mips_cpu_info): Rename vr4121 to vr4120.
* config/mips/mips.md: Apply same renaming here.
2002-10-01 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (PROCESSOR_R4320, TARGET_MIPS4320): Remove.
(GENERATE_MULT3_SI): Remove use of TARGET_MIPS4320.
* config/mips/mips.c (mips_cpu_info): Remove vr4320 entry.
* config/mips/mips.md (define_attr cpu): Remove r4320.
Remove vr4320 scheduler and uses of TARGET_MIPS4320.
2002-10-01 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.c (mips16_strings): New variable.
(mips_output_function_epilogue): Clear the SYMBOL_REF_FLAG of every
symbol in mips16_strings. Free the list.
(mips_encode_section_info): Keep track of local strings.
2002-10-01 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (bunge, bltgt, bungt): New define_expands.
(sordered_df, sordered_sf): Remove.
* config/mips/mips.c (get_float_compare_codes): New fn.
(gen_int_relational, gen_conditional_move): Use it.
2002-10-01 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips-protos.h (mips_emit_fcc_reload): Declare.
* config/mips/mips.h (PREDICATE_CODES): Add fcc_register_operand.
* config/mips/mips.c (fcc_register_operand): New function.
(mips_emit_fcc_reload): New function, extracted from reload_incc.
(override_options): Allow TFmode values in float registers
if ISA_HAS_8CC.
* cnfig/mips/mips.md (reload_incc): Change destination prediate
to fcc_register_operand. Remove misleading source constraint.
Use mips_emit_fcc_reload.
(reload_outcc): Duplicate reload_incc.
2003-04-30 Diego Novillo <dnovillo@redhat.com>
* builtins.def (BUILTIN_CONSTANT_P): Mark as constant.
@ -24,7 +583,7 @@
* tree.h (DECL_POINTER_DEPTH): Remove.
(struct tree_decl): Remove pointer_depth.
2003-04-30 Janis Johnson <janis187@us.ibm.com>
* config/rs6000/linux64.h (ASM_OUTPUT_LABELREF): Remove.
@ -128,7 +687,7 @@
2003-04-29 Jason Merrill <jason@redhat.com>
PR middle-end/10336
* jump.c (never_reached_warning): Really stop looking if we reach
* jump.c (never_reached_warning): Really stop looking if we reach
the beginning of the function.
2003-04-29 Bob Wilson <bob.wilson@acm.org>

12
gcc/combine.c
View File

@ -1437,7 +1437,7 @@ cant_combine_insn_p (insn)
/* Never combine loads and stores involving hard regs that are likely
to be spilled. The register allocator can usually handle such
reg-reg moves by tying. If we allow the combiner to make
reg-reg moves by tying. If we allow the combiner to make
substitutions of likely-spilled regs, we may abort in reload.
As an exception, we allow combinations involving fixed regs; these are
not available to the register allocator so there's no risk involved. */
@ -10159,6 +10159,14 @@ gen_lowpart_for_combine (mode, x)
if (GET_MODE (x) == mode)
return x;
/* Return identity if this is a CONST or symbolic
reference. */
if (mode == Pmode
&& (GET_CODE (x) == CONST
|| GET_CODE (x) == SYMBOL_REF
|| GET_CODE (x) == LABEL_REF))
return x;
/* We can only support MODE being wider than a word if X is a
constant integer or has a mode the same size. */
@ -10242,6 +10250,8 @@ gen_lowpart_for_combine (mode, x)
{
sub_mode = int_mode_for_mode (mode);
x = gen_lowpart_common (sub_mode, x);
if (x == 0)
return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
}
res = simplify_gen_subreg (mode, x, sub_mode, offset);
if (res)

2
gcc/config/mips/5400.md
View File

@ -64,7 +64,7 @@
(define_insn_reservation "ir_vr54_arith" 1
(and (eq_attr "cpu" "r5400")
(eq_attr "type" "arith,darith,icmp,nop"))
(eq_attr "type" "arith,darith,const,icmp,nop"))
"vr54_dp0|vr54_dp1")
(define_insn_reservation "ir_vr54_imul_si" 3

2
gcc/config/mips/5500.md
View File

@ -57,7 +57,7 @@
(define_insn_reservation "ir_vr55_arith" 1
(and (eq_attr "cpu" "r5500")
(eq_attr "type" "arith,darith,icmp,nop"))
(eq_attr "type" "arith,darith,const,icmp,nop"))
"vr55_dp0|vr55_dp1")
(define_insn_reservation "ir_vr55_imul_si" 3

5
gcc/config/mips/elf.h
View File

@ -234,12 +234,7 @@ void FN () \
#define LIB_SPEC ""
#undef STARTFILE_SPEC
#if defined(HAVE_MIPS_LIBGLOSS_STARTUP_DIRECTIVES) \
|| (MIPS_ABI_DEFAULT == ABI_MEABI)
#define STARTFILE_SPEC "crti%O%s crtbegin%O%s"
#else
#define STARTFILE_SPEC "crti%O%s crtbegin%O%s %{!mno-crt0:crt0%O%s}"
#endif
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend%O%s crtn%O%s"

5
gcc/config/mips/elf64.h
View File

@ -192,12 +192,7 @@ void FN () \
#define LIB_SPEC ""
#undef STARTFILE_SPEC
#if defined(HAVE_MIPS_LIBGLOSS_STARTUP_DIRECTIVES) \
|| (MIPS_ABI_DEFAULT == ABI_MEABI)
#define STARTFILE_SPEC "crti%O%s crtbegin%O%s"
#else
#define STARTFILE_SPEC "crti%O%s crtbegin%O%s %{!mno-crt0:crt0%O%s}"
#endif
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend%O%s crtn%O%s"

2
gcc/config/mips/linux.h
View File

@ -127,7 +127,7 @@ void FN () \
builtin_define_std ("linux"); \
builtin_assert ("system=linux"); \
/* The GNU C++ standard library requires this. */ \
if (c_language = clk_cplusplus) \
if (c_language == clk_cplusplus) \
builtin_define ("_GNU_SOURCE"); \
\
if (mips_abi == ABI_N32) \

32
gcc/config/mips/mips-protos.h
View File

@ -39,7 +39,7 @@ extern int mips_can_use_return_insn PARAMS ((void));
extern void mips_declare_object PARAMS ((FILE *, const char *,
const char *,
const char *, int));
extern void mips_expand_epilogue PARAMS ((void));
extern void mips_expand_epilogue PARAMS ((int));
extern void mips_expand_prologue PARAMS ((void));
extern void mips_output_filename PARAMS ((FILE *, const char *));
extern void mips_output_lineno PARAMS ((FILE *, int));
@ -81,6 +81,12 @@ extern void mips_va_start PARAMS ((tree, rtx));
extern struct rtx_def *mips_va_arg PARAMS ((tree, tree));
extern void expand_block_move PARAMS ((rtx *));
extern bool mips_expand_unaligned_load PARAMS ((rtx, rtx,
unsigned int,
int));
extern bool mips_expand_unaligned_store PARAMS ((rtx, rtx,
unsigned int,
int));
extern void final_prescan_insn PARAMS ((rtx, rtx *, int));
extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *,
tree, rtx));
@ -91,13 +97,11 @@ extern void mips_set_return_address PARAMS ((rtx, rtx));
extern void machine_dependent_reorg PARAMS ((rtx));
extern void mips_count_memory_refs PARAMS ((rtx, int));
extern HOST_WIDE_INT mips_debugger_offset PARAMS ((rtx, HOST_WIDE_INT));
extern int mips_check_split PARAMS ((rtx, enum machine_mode));
extern const char *mips_fill_delay_slot PARAMS ((const char *,
enum delay_type, rtx *,
rtx));
extern const char *mips_move_1word PARAMS ((rtx *, rtx, int));
extern const char *mips_move_2words PARAMS ((rtx *, rtx));
extern const char *mips_sign_extend PARAMS ((rtx, rtx, rtx));
extern const char *mips_emit_prefetch PARAMS ((rtx *));
extern const char *mips_restore_gp PARAMS ((rtx *, rtx));
extern const char *output_block_move PARAMS ((rtx, rtx *, int,
@ -106,12 +110,7 @@ extern void override_options PARAMS ((void));
extern void mips_conditional_register_usage PARAMS ((void));
extern void print_operand_address PARAMS ((FILE *, rtx));
extern void print_operand PARAMS ((FILE *, rtx, int));
extern int double_memory_operand PARAMS ((rtx,enum machine_mode));
extern struct rtx_def * embedded_pic_offset PARAMS ((rtx));
extern struct rtx_def * mips16_gp_offset PARAMS ((rtx));
extern int mips16_gp_offset_p PARAMS ((rtx));
extern int mips16_constant PARAMS ((rtx, enum machine_mode,
int, int));
extern int build_mips16_call_stub PARAMS ((rtx, rtx, rtx, int));
extern const char *mips_output_conditional_branch PARAMS ((rtx, rtx *,
int, int, int,
@ -120,7 +119,7 @@ extern int mips_adjust_insn_length PARAMS ((rtx, int));
extern enum reg_class mips_secondary_reload_class PARAMS ((enum reg_class,
enum machine_mode,
rtx, int));
extern bool mips_cannot_change_mode_class
extern bool mips_cannot_change_mode_class
PARAMS ((enum machine_mode, enum machine_mode,
enum reg_class));
extern int mips_class_max_nregs PARAMS ((enum reg_class,
@ -129,13 +128,21 @@ extern int mips_register_move_cost PARAMS ((enum machine_mode,
enum reg_class,
enum reg_class));
extern int pic_address_needs_scratch PARAMS ((rtx));
extern int se_arith_operand PARAMS ((rtx, enum machine_mode));
extern int coprocessor_operand PARAMS ((rtx, enum machine_mode));
extern int coprocessor2_operand PARAMS ((rtx, enum machine_mode));
extern int symbolic_operand PARAMS ((rtx, enum machine_mode));
extern int mips_legitimate_address_p PARAMS ((enum machine_mode,
extern int mips_address_insns PARAMS ((rtx, enum machine_mode));
extern int mips_fetch_insns PARAMS ((rtx));
extern int mips_const_insns PARAMS ((rtx));
extern bool mips_global_pic_constant_p PARAMS ((rtx));
extern bool mips_legitimate_address_p PARAMS ((enum machine_mode,
rtx, int));
extern bool mips_legitimize_address PARAMS ((rtx *,
enum machine_mode));
extern bool mips_legitimize_move PARAMS ((enum machine_mode,
rtx, rtx));
extern rtx mips_simplify_dwarf_addr PARAMS ((rtx));
extern void mips_expand_call PARAMS ((rtx, rtx, rtx, rtx, int));
extern int mips_reg_mode_ok_for_base_p PARAMS ((rtx,
enum machine_mode,
int));
@ -165,5 +172,6 @@ extern rtx gen_int_relational PARAMS ((enum rtx_code, rtx, rtx,
rtx,int *));
extern void gen_conditional_branch PARAMS ((rtx *, enum rtx_code));
#endif
extern rtx mips_return_addr PARAMS ((int, rtx));
#endif /* ! GCC_MIPS_PROTOS_H */

3570
gcc/config/mips/mips.c
View File

File diff suppressed because it is too large Load Diff

536
gcc/config/mips/mips.h
View File

@ -92,17 +92,6 @@ enum processor_type {
#define ABI_64 2
#define ABI_EABI 3
#define ABI_O64 4
/* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
which is not the same as the above EABI (defined by Cygnus,
Greenhills, and Toshiba?). MEABI is not yet complete or published,
but at this point it looks like N32 as far as calling conventions go,
but allows for either 32 or 64 bit registers.
Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
EABI the legacy EABI. In the end we may end up calling both ABI's
EABI but give them different version numbers, but for now I'm going
with different names. */
#define ABI_MEABI 5
/* Whether to emit abicalls code sequences or not. */
@ -175,7 +164,6 @@ extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
extern const char *mips_entry_string; /* for -mentry */
extern const char *mips_no_mips16_string;/* for -mno-mips16 */
extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
extern int mips_split_addresses; /* perform high/lo_sum support */
extern int dslots_load_total; /* total # load related delay slots */
extern int dslots_load_filled; /* # filled load delay slots */
extern int dslots_jump_total; /* total # jump related delay slots */
@ -240,6 +228,7 @@ extern void sbss_section PARAMS ((void));
multiply-add operations. */
#define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
instructions. */
#define MASK_EXPLICIT_RELOCS 0x04000000 /* Use relocation operators. */
/* Debug switches, not documented */
#define MASK_DEBUG 0 /* unused */
@ -332,12 +321,50 @@ extern void sbss_section PARAMS ((void));
#define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
/* True if we should use NewABI-style relocation operators for
symbolic addresses. This is never true for mips16 code,
which has its own conventions. */
#define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
/* This is true if we must enable the assembly language file switching
code. */
#define TARGET_FILE_SWITCHING \
(TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
/* True if the call patterns should be split into a jalr followed by
an instruction to restore $gp. This is only ever true for SVR4 PIC,
in which $gp is call-clobbered. It is only safe to split the load
from the call when every use of $gp is explicit. */
#define TARGET_SPLIT_CALLS \
(TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
/* True if we can optimize sibling calls. For simplicity, we only
handle cases in which call_insn_operand will reject invalid
sibcall addresses. There are two cases in which this isn't true:
- TARGET_MIPS16. call_insn_operand accepts constant addresses
but there is no direct jump instruction. It isn't worth
using sibling calls in this case anyway; they would usually
be longer than normal calls.
- TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
accepts global constants, but "jr $25" is the only allowed
sibcall. */
#define TARGET_SIBCALLS \
(!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
/* True if .gpword or .gpdword should be used for switch tables.
Not all SGI assemblers support this. */
#define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
/* We must disable the function end stabs when doing the file switching trick,
because the Lscope stabs end up in the wrong place, making it impossible
to debug the resulting code. */
@ -379,6 +406,8 @@ extern void sbss_section PARAMS ((void));
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
#define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
/* Define preprocessor macros for the -march and -mtune options.
PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
processor. If INFO's canonical name is "foo", define PREFIX to
@ -534,9 +563,7 @@ extern void sbss_section PARAMS ((void));
#define TARGET_SWITCHES \
{ \
SUBTARGET_TARGET_SWITCHES \
{"no-crt0", 0, \
N_("No default crt0.o") }, \
SUBTARGET_TARGET_SWITCHES \
{"int64", MASK_INT64 | MASK_LONG64, \
N_("Use 64-bit int type")}, \
{"long64", MASK_LONG64, \
@ -639,6 +666,10 @@ extern void sbss_section PARAMS ((void));
N_("Use Branch Likely instructions, overriding default for arch")}, \
{ "no-branch-likely", -MASK_BRANCHLIKELY, \
N_("Don't use Branch Likely instructions, overriding default for arch")}, \
{"explicit-relocs", MASK_EXPLICIT_RELOCS, \
N_("Use NewABI-style %reloc() assembly operators")}, \
{"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
N_("Use assembler macros instead of relocation operators")}, \
{"debug", MASK_DEBUG, \
NULL}, \
{"debuga", MASK_DEBUG_A, \
@ -808,6 +839,10 @@ extern void sbss_section PARAMS ((void));
/* Likewise for 32-bit regs. */
#define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
/* True if symbols are 64 bits wide. At present, n64 is the only
ABI for which this is true. */
#define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
|| ISA_MIPS4 \
@ -893,7 +928,8 @@ extern void sbss_section PARAMS ((void));
)
/* ISA has three operand multiply instructions that the result
from a 4th operand and puts the result in an accumulator. */
#define ISA_HAS_MACC (TARGET_MIPS5400 \
#define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
)
@ -1029,12 +1065,6 @@ extern int mips_abi;
#define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
#endif
#if MIPS_ABI_DEFAULT == ABI_MEABI
/* Most GAS don't know about MEABI. */
#define MULTILIB_ABI_DEFAULT "mabi=meabi"
#define ASM_ABI_DEFAULT_SPEC ""
#endif
/* Only ELF targets can switch the ABI. */
#ifndef OBJECT_FORMAT_ELF
#undef ASM_ABI_DEFAULT_SPEC
@ -1318,6 +1348,8 @@ extern int mips_abi;
SFmode register saves. */
#define DWARF_CIE_DATA_ALIGNMENT 4
#define ASM_SIMPLIFY_DWARF_ADDR mips_simplify_dwarf_addr
/* Overrides for the COFF debug format. */
#define PUT_SDB_SCL(a) \
do { \
@ -1587,20 +1619,19 @@ do { \
# endif
#endif
/* Width in bits of a pointer.
See also the macro `Pmode' defined below. */
/* Width in bits of a pointer. */
#ifndef POINTER_SIZE
#define POINTER_SIZE (Pmode == DImode ? 64 : 32)
#define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
#endif
/* Allocation boundary (in *bits*) for storing pointers in memory. */
#define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
#define POINTERS_EXTEND_UNSIGNED 0
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
#define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
|| mips_abi == ABI_64 \
|| (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
/* Allocation boundary (in *bits*) for the code of a function. */
#define FUNCTION_BOUNDARY 32
@ -1678,9 +1709,7 @@ do { \
/* Force right-alignment for small varargs in 32 bit little_endian mode */
#define PAD_VARARGS_DOWN (TARGET_64BIT \
|| mips_abi == ABI_MEABI \
? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
#define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
/* Define this macro if an argument declared as `char' or `short' in a
prototype should actually be passed as an `int'. In addition to
@ -1708,26 +1737,28 @@ do { \
in a wider mode than that declared by the program. In such cases,
the value is constrained to be within the bounds of the declared
type, but kept valid in the wider mode. The signedness of the
extension may differ from that of the type.
We promote any value smaller than SImode up to SImode. We don't
want to promote to DImode when in 64 bit mode, because that would
prevent us from using the faster SImode multiply and divide
instructions. */
extension may differ from that of the type. */
#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
if (GET_MODE_CLASS (MODE) == MODE_INT \
&& GET_MODE_SIZE (MODE) < 4) \
(MODE) = SImode;
&& GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
{ \
if ((MODE) == SImode) \
(UNSIGNEDP) = 0; \
(MODE) = Pmode; \
}
/* Define if loading short immediate values into registers sign extends. */
#define SHORT_IMMEDIATES_SIGN_EXTEND
/* Define this if function arguments should also be promoted using the above
procedure. */
#define PROMOTE_FUNCTION_ARGS
/* Likewise, if the function return value is promoted. */
#define PROMOTE_FUNCTION_RETURN
/* Standard register usage. */
@ -1764,10 +1795,10 @@ do { \
#define FIXED_REGISTERS \
{ \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
/* COP0 registers */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
@ -1780,20 +1811,22 @@ do { \
}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
registers that can be used without being saved.
The latter must include the registers where values are returned
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like. */
/* Don't mark $31 as a call-clobbered register. The idea is that
it's really the call instructions themselves which clobber $31.
We don't care what the called function does with it afterwards.
This approach makes it easier to implement sibcalls. Unlike normal
calls, sibcalls don't clobber $31, so the register reaches the
called function in tact. EPILOGUE_USES says that $31 is useful
to the called function. */
#define CALL_USED_REGISTERS \
{ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* COP0 registers */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
@ -1817,12 +1850,12 @@ do { \
#define CALL_REALLY_USED_REGISTERS \
{ /* General registers. */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
/* Floating-point registers. */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* Others. */ \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/* COP0 registers */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@ -1857,8 +1890,8 @@ do { \
#define ST_REG_LAST 74
#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
#define RAP_REG_NUM 75
/* FIXME: renumber. */
#define COP0_REG_FIRST 80
#define COP0_REG_LAST 111
#define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
@ -1978,10 +2011,6 @@ extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
/* Base register for access to arguments of the function. */
#define ARG_POINTER_REGNUM GP_REG_FIRST
/* Fake register that holds the address on the stack of the
current function's return address. */
#define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
/* Register in which static-chain is passed to a function. */
#define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
@ -2052,6 +2081,8 @@ enum reg_class
M16_REGS, /* mips16 directly accessible registers */
T_REG, /* mips16 T register ($24) */
M16_T_REGS, /* mips16 registers plus T register */
PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
LEA_REGS, /* Every GPR except $25 */
GR_REGS, /* integer registers */
FP_REGS, /* floating point registers */
HI_REG, /* hi register */
@ -2090,6 +2121,8 @@ enum reg_class
"M16_REGS", \
"T_REG", \
"M16_T_REGS", \
"PIC_FN_ADDR_REG", \
"LEA_REGS", \
"GR_REGS", \
"FP_REGS", \
"HI_REG", \
@ -2131,6 +2164,8 @@ enum reg_class
{ 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
{ 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
{ 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
{ 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
{ 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
{ 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
@ -2187,7 +2222,8 @@ extern const enum reg_class mips_regno_to_class[];
/* This macro is used later on in the file. */
#define GR_REG_CLASS_P(CLASS) \
((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
|| (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
|| (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
|| (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
/* This macro is also used later on in the file. */
#define COP_REG_CLASS_P(CLASS) \
@ -2246,6 +2282,35 @@ extern enum reg_class mips_char_to_class[256];
#define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
/* True if VALUE is a signed 16-bit number. */
#define SMALL_OPERAND(VALUE) \
((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
/* True if VALUE is an unsigned 16-bit number. */
#define SMALL_OPERAND_UNSIGNED(VALUE) \
(((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
/* True if VALUE can be loaded into a register using LUI. */
#define LUI_OPERAND(VALUE) \
(((VALUE) | 0x7fff0000) == 0x7fff0000 \
|| ((VALUE) | 0x7fff0000) + 0x10000 == 0)
/* Return a value X with the low 16 bits clear, and such that
VALUE - X is a signed 16-bit value. */
#define CONST_HIGH_PART(VALUE) \
(((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
#define CONST_LOW_PART(VALUE) \
((VALUE) - CONST_HIGH_PART (VALUE))
#define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
#define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
#define LUI_INT(X) LUI_OPERAND (INTVAL (X))
/* The letters I, J, K, L, M, N, O, and P in a register constraint
string can be used to stand for particular ranges of immediate
operands. This macro defines what the ranges are. C is the
@ -2274,21 +2339,14 @@ extern enum reg_class mips_char_to_class[256];
`P' is used for positive 16 bit constants. */
#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
((C) == 'I' ? SMALL_OPERAND (VALUE) \
: (C) == 'J' ? ((VALUE) == 0) \
: (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
: (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
&& (((VALUE) & ~2147483647) == 0 \
|| ((VALUE) & ~2147483647) == ~2147483647)) \
: (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
&& (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
&& (((VALUE) & 0x0000ffff) != 0 \
|| (((VALUE) & ~2147483647) != 0 \
&& ((VALUE) & ~2147483647) != ~2147483647))) \
: (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
: (C) == 'L' ? LUI_OPERAND (VALUE) \
: (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
&& !SMALL_OPERAND_UNSIGNED (VALUE) \
&& !LUI_OPERAND (VALUE)) \
: (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
: (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
: (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
@ -2305,22 +2363,40 @@ extern enum reg_class mips_char_to_class[256];
((C) == 'G' \
&& (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
/* True if OP is a constant that should not be moved into $25.
We need this because many versions of gas treat 'la $25,foo' as
part of a call sequence and allow a global 'foo' to be lazily bound. */
#define DANGEROUS_FOR_LA25_P(OP) \
(TARGET_ABICALLS \
&& !TARGET_EXPLICIT_RELOCS \
&& mips_global_pic_constant_p (OP))
/* Letters in the range `Q' through `U' may be defined in a
machine-dependent fashion to stand for arbitrary operand types.
The machine description macro `EXTRA_CONSTRAINT' is passed the
operand as its first argument and the constraint letter as its
second operand.
`Q' is for mips16 GP relative constants
`R' is for memory references which take 1 word for the instruction.
`T' is for memory addresses that can be used to load two words. */
`Q' is for signed 16-bit constants.
`R' is for single-instruction memory references. Note that this
constraint has often been used in linux and glibc code.
`S' is for legitimate constant call addresses.
`T' is for constant move_operands that cannot be safely loaded into $25.
`U' is for constant move_operands that can be safely loaded into $25. */
#define EXTRA_CONSTRAINT(OP,CODE) \
(((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
: ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
&& mips16_gp_offset_p (OP)) \
: (GET_CODE (OP) != MEM) ? FALSE \
: ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
(((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
: ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
&& mips_fetch_insns (OP) == 1) \
: ((CODE) == 'S') ? (CONSTANT_P (OP) \
&& call_insn_operand (OP, VOIDmode)) \
: ((CODE) == 'T') ? (CONSTANT_P (OP) \
&& move_operand (OP, VOIDmode) \
&& DANGEROUS_FOR_LA25_P (OP)) \
: ((CODE) == 'U') ? (CONSTANT_P (OP) \
&& move_operand (OP, VOIDmode) \
&& !DANGEROUS_FOR_LA25_P (OP)) \
: FALSE)
/* Given an rtx X being reloaded into a reg required to be
@ -2430,20 +2506,7 @@ extern enum reg_class mips_char_to_class[256];
during reload to be either the frame pointer or the stack pointer plus
an offset. */
/* ??? This definition fails for leaf functions. There is currently no
general solution for this problem. */
/* ??? There appears to be no way to get the return address of any previous
frame except by disassembling instructions in the prologue/epilogue.
So currently we support only the current frame. */
#define RETURN_ADDR_RTX(count, frame) \
(((count) == 0) \
? (leaf_function_p () \
? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
: gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
RETURN_ADDRESS_POINTER_REGNUM))) \
: (rtx) 0)
#define RETURN_ADDR_RTX mips_return_addr
/* Since the mips16 ISA mode is encoded in the least-significant bit
of the address, mask it off return addresses for purposes of
@ -2451,6 +2514,7 @@ extern enum reg_class mips_char_to_class[256];
#define MASK_RETURN_ADDR GEN_INT (-2)
/* Similarly, don't use the least-significant bit to tell pointers to
code from vtable index. */
@ -2489,9 +2553,6 @@ extern enum reg_class mips_char_to_class[256];
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
{ ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
{ RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
{ RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
{ FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
@ -2517,15 +2578,11 @@ extern enum reg_class mips_char_to_class[256];
*/
#define CAN_ELIMINATE(FROM, TO) \
(((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
&& (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \
|| (TO) == HARD_FRAME_POINTER_REGNUM)) \
|| ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
&& ((TO) == HARD_FRAME_POINTER_REGNUM \
(((TO) == HARD_FRAME_POINTER_REGNUM \
|| ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
&& ! (TARGET_MIPS16 && TARGET_64BIT) \
&& (! TARGET_MIPS16 \
|| compute_frame_size (get_frame_size ()) < 32768)))))
|| compute_frame_size (get_frame_size ()) < 32768))))
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
(OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
@ -2892,6 +2949,11 @@ typedef struct mips_args {
|| (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
|| (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
/* Say that the epilogue uses the return address register. Note that
in the case of sibcalls, the values "used by the epilogue" are
considered live at the start of the called function. */
#define EPILOGUE_USES(REGNO) ((REGNO) == 31)
/* Treat LOC as a byte offset from the stack pointer and round it up
to the next fully-aligned offset. */
#define MIPS_STACK_ALIGN(LOC) \
@ -2959,7 +3021,7 @@ typedef struct mips_args {
fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
if (Pmode == DImode) \
if (ptr_mode == DImode) \
{ \
fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
@ -2972,7 +3034,7 @@ typedef struct mips_args {
fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
if (Pmode == DImode) \
if (ptr_mode == DImode) \
{ \
fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
@ -2987,11 +3049,11 @@ typedef struct mips_args {
/* A C expression for the size in bytes of the trampoline, as an
integer. */
#define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
#define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
/* Alignment required for trampolines, in bits. */
#define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
#define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
/* INITIALIZE_TRAMPOLINE calls this library function to flush
program and data caches. */
@ -3008,24 +3070,21 @@ typedef struct mips_args {
#define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
{ \
rtx addr = ADDR; \
if (Pmode == DImode) \
{ \
emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
} \
else \
{ \
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
} \
rtx func_addr, chain_addr; \
\
func_addr = plus_constant (ADDR, 32); \
chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
\
/* Flush both caches. We need to flush the data cache in case \
the system has a write-back cache. */ \
/* ??? Should check the return value for errors. */ \
if (mips_cache_flush_func && mips_cache_flush_func[0]) \
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
0, VOIDmode, 3, addr, Pmode, \
0, VOIDmode, 3, ADDR, Pmode, \
GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
GEN_INT (3), TYPE_MODE (integer_type_node)); \
}
@ -3113,32 +3172,12 @@ typedef struct mips_args {
}
#endif
/* A C expression that is 1 if the RTX X is a constant which is a
valid address. This is defined to be the same as `CONSTANT_P (X)',
but rejecting CONST_DOUBLE. */
/* When pic, we must reject addresses of the form symbol+large int.
This is because an instruction `sw $4,s+70000' needs to be converted
by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
assembler would use $at as a temp to load in the large offset. In this
case $at is already in use. We convert such problem addresses to
`la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
/* ??? SGI Irix 6 assembler fails for CONST address, so reject them
when !TARGET_GAS. */
/* We should be rejecting everything but const addresses. */
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST \
&& ! (flag_pic && pic_address_needs_scratch (X)) \
&& (TARGET_GAS) \
&& (mips_abi != ABI_N32 \
&& mips_abi != ABI_64)))
/* Check for constness inline but use mips_legitimate_address_p
to check whether a constant really is an address. */
#define CONSTANT_ADDRESS_P(X) \
(CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
/* Define this, so that when PIC, reload won't try to reload invalid
addresses which require two reload registers. */
#define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
/* Nonzero if the constant value X is a legitimate general operand.
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
@ -3153,130 +3192,13 @@ typedef struct mips_args {
gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
ABI_64 to work together, we'll need to fix this. */
#define LEGITIMATE_CONSTANT_P(X) \
((GET_CODE (X) != CONST_DOUBLE \
|| mips_const_double_ok (X, GET_MODE (X))) \
&& ! (GET_CODE (X) == CONST \
&& ! TARGET_GAS \
&& (mips_abi == ABI_N32 \
|| mips_abi == ABI_64)) \
&& (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
#define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
/* A C compound statement that attempts to replace X with a valid
memory address for an operand of mode MODE. WIN will be a C
statement label elsewhere in the code; the macro definition may
use
GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
to avoid further processing if the address has become legitimate.
X will always be the result of a call to `break_out_memory_refs',
and OLDX will be the operand that was given to that function to
produce X.
The code generated by this macro should not alter the
substructure of X. If it transforms X into a more legitimate
form, it should assign X (which will always be a C variable) a
new value.
It is not necessary for this macro to come up with a legitimate
address. The compiler has standard ways of doing so in all
cases. In fact, it is safe for this macro to do nothing. But
often a machine-dependent strategy can generate better code.
For the MIPS, transform:
memory(X + <large int>)
into:
Y = <large int> & ~0x7fff;
Z = X + Y
memory (Z + (<large int> & 0x7fff));
This is for CSE to find several similar references, and only use one Z.
When PIC, convert addresses of the form memory (symbol+large int) to
memory (reg+large int). */
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
{ \
register rtx xinsn = (X); \
\
if (TARGET_DEBUG_B_MODE) \
{ \
GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
GO_DEBUG_RTX (xinsn); \
} \
\
if (mips_split_addresses && mips_check_split (X, MODE)) \
{ \
/* ??? Is this ever executed? */ \
X = gen_rtx_LO_SUM (Pmode, \
copy_to_mode_reg (Pmode, \
gen_rtx (HIGH, Pmode, X)), \
X); \
goto WIN; \
} \
\
if (GET_CODE (xinsn) == CONST \
&& ((flag_pic && pic_address_needs_scratch (xinsn)) \
/* ??? SGI's Irix 6 assembler can't handle CONST. */ \
|| (!TARGET_GAS \
&& (mips_abi == ABI_N32 \
|| mips_abi == ABI_64)))) \
{ \
rtx ptr_reg = gen_reg_rtx (Pmode); \
rtx constant = XEXP (XEXP (xinsn, 0), 1); \
\
emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
\
X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
if (SMALL_INT (constant)) \
goto WIN; \
/* Otherwise we fall through so the code below will fix the \
constant. */ \
xinsn = X; \
} \
\
if (GET_CODE (xinsn) == PLUS) \
{ \
register rtx xplus0 = XEXP (xinsn, 0); \
register rtx xplus1 = XEXP (xinsn, 1); \
register enum rtx_code code0 = GET_CODE (xplus0); \
register enum rtx_code code1 = GET_CODE (xplus1); \
\
if (code0 != REG && code1 == REG) \
{ \
xplus0 = XEXP (xinsn, 1); \
xplus1 = XEXP (xinsn, 0); \
code0 = GET_CODE (xplus0); \
code1 = GET_CODE (xplus1); \
} \
\
if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
&& code1 == CONST_INT && !SMALL_INT (xplus1)) \
{ \
rtx int_reg = gen_reg_rtx (Pmode); \
rtx ptr_reg = gen_reg_rtx (Pmode); \
\
emit_move_insn (int_reg, \
GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
\
emit_insn (gen_rtx_SET (VOIDmode, \
ptr_reg, \
gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
\
X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
goto WIN; \
} \
} \
\
if (TARGET_DEBUG_B_MODE) \
GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
}
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
do { \
if (mips_legitimize_address (&(X), MODE)) \
goto WIN; \
} while (0)
/* A C statement or compound statement with a conditional `goto
@ -3311,7 +3233,6 @@ typedef struct mips_args {
#define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
mips_string_length = 0;
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction.
@ -3319,7 +3240,7 @@ typedef struct mips_args {
overflow is no more likely than the overflow in a branch
instruction. Large functions can currently break in both ways. */
#define CASE_VECTOR_MODE \
(TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
(TARGET_MIPS16 ? HImode : ptr_mode)
/* Define as C expression which evaluates to nonzero if the tablejump
instruction expects the table to contain offsets from the address of the
@ -3358,32 +3279,29 @@ typedef struct mips_args {
/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
is done just by pretending it is already truncated. */
/* In 64 bit mode, 32 bit instructions require that register values be properly
sign-extended to 64 bits. As a result, a truncate is not a no-op if it
converts a value >32 bits to a value <32 bits. */
/* ??? This results in inefficient code for 64 bit to 32 conversions.
Something needs to be done about this. Perhaps not use any 32 bit
instructions? Perhaps use PROMOTE_MODE? */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
(TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode.
For MIPS we make pointers are the smaller of longs and gp-registers. */
between pointers and any other objects of this machine mode. */
#ifndef Pmode
#define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
#define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
#endif
/* A function address in a call instruction
is a word address (for indexing purposes)
so give the MEM rtx a words's mode. */
/* Give call MEMs SImode since it is the "most permissive" mode
for both 32-bit and 64-bit targets. */
#define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
#define FUNCTION_MODE SImode
/* The cost of loading values from the constant pool. It should be
larger than the cost of any constant we want to synthesise in-line. */
#define CONSTANT_POOL_COST COSTS_N_INSNS (8)
/* A C expression for the cost of moving data from a register in
class FROM to one in class TO. The classes are expressed using
the enumeration values such as `GENERAL_REGS'. A value of 2 is
@ -3456,12 +3374,12 @@ typedef struct mips_args {
#define PREDICATE_CODES \
{"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
{"arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
{"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
{"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
ADDRESSOF }}, \
{"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
ADDRESSOF }}, \
{"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
{"const_arith_operand", { CONST, CONST_INT }}, \
{"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
{"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
{"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
{"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
{"small_int", { CONST_INT }}, \
{"large_int", { CONST_INT }}, \
{"mips_const_double_ok", { CONST_DOUBLE }}, \
@ -3472,29 +3390,13 @@ typedef struct mips_args {
LTU, LEU }}, \
{"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
{"pc_or_label_operand", { PC, LABEL_REF }}, \
{"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
{"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
{"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF, SUBREG, \
REG, MEM, ADDRESSOF }}, \
{"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF, SUBREG, \
REG, MEM, ADDRESSOF, SIGN_EXTEND }}, \
{"se_register_operand", { SUBREG, REG, ADDRESSOF, \
SIGN_EXTEND }}, \
{"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
ADDRESSOF, SIGN_EXTEND }}, \
{"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
ADDRESSOF, SIGN_EXTEND }}, \
{"se_arith_operand", { REG, CONST_INT, SUBREG, \
ADDRESSOF, SIGN_EXTEND }}, \
{"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
SYMBOL_REF, LABEL_REF, SUBREG, \
REG, ADDRESSOF, SIGN_EXTEND }}, \
REG, MEM}}, \
{"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
CONST_DOUBLE, CONST }}, \
{"fcc_register_operand", { REG, SUBREG }}, \
{"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
{"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
{"fcc_register_operand", { REG, SUBREG }},
/* A list of predicates that do special things with modes, and so
should not elicit warnings for VOIDmode match_operand. */
@ -4068,7 +3970,7 @@ do { \
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
fprintf (STREAM, "\t%s\t%sL%d\n", \
Pmode == DImode ? ".dword" : ".word", \
ptr_mode == DImode ? ".dword" : ".word", \
LOCAL_LABEL_PREFIX, \
VALUE)
@ -4083,17 +3985,15 @@ do { \
LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
else if (TARGET_EMBEDDED_PIC) \
fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
Pmode == DImode ? ".dword" : ".word", \
ptr_mode == DImode ? ".dword" : ".word", \
LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
else if (mips_abi == ABI_32 || mips_abi == ABI_O64 \
|| (TARGET_GAS && mips_abi == ABI_N32) \
|| (TARGET_GAS && mips_abi == ABI_64)) \
else if (TARGET_GPWORD) \
fprintf (STREAM, "\t%s\t%sL%d\n", \
Pmode == DImode ? ".gpdword" : ".gpword", \
ptr_mode == DImode ? ".gpdword" : ".gpword", \
LOCAL_LABEL_PREFIX, VALUE); \
else \
fprintf (STREAM, "\t%s\t%sL%d\n", \
Pmode == DImode ? ".dword" : ".word", \
ptr_mode == DImode ? ".dword" : ".word", \
LOCAL_LABEL_PREFIX, VALUE); \
} while (0)
@ -4244,11 +4144,13 @@ while (0)
/* Default definitions for size_t and ptrdiff_t. We must override the
definitions from ../svr4.h on mips-*-linux-gnu. */
#undef SIZE_TYPE
#define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
#ifndef SIZE_TYPE
#define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
#endif
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
#ifndef PTRDIFF_TYPE
#define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
#endif
/* See mips_expand_prologue's use of loadgp for when this should be
true. */

3840
gcc/config/mips/mips.md
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File diff suppressed because it is too large Load Diff

2
gcc/config/mips/sr71k.md
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@ -206,7 +206,7 @@
(define_insn_reservation "ir_sr70_arith"
1
(and (eq_attr "cpu" "sr71000")
(eq_attr "type" "arith,darith"))
(eq_attr "type" "arith,darith,const"))
"ri_insns")
;; emulate repeat (dispatch stall) by spending extra cycle(s) in

6
gcc/config/mips/t-elf
View File

@ -31,9 +31,9 @@ TARGET_LIBGCC2_CFLAGS = -G 0
# Build the libraries for both hard and soft floating point
MULTILIB_OPTIONS = msoft-float EL/EB
MULTILIB_DIRNAMES = soft-float el eb
MULTILIB_MATCHES = EL=mel EB=meb
#MULTILIB_OPTIONS = msoft-float EL/EB
#MULTILIB_DIRNAMES = soft-float el eb
#MULTILIB_MATCHES = EL=mel EB=meb
#MULTILIB_MATCHES = msingle-float=m4650
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o

13488
gcc/configure vendored
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File diff suppressed because it is too large Load Diff

17
gcc/configure.in
View File

@ -2600,6 +2600,23 @@ case "$target" in
[Define if your MIPS libgloss linker scripts consistently include STARTUP directives.])
fi
AC_MSG_RESULT($gcc_cv_mips_libgloss_startup)
AC_MSG_CHECKING(whether the assembler has explicit relocation support)
if test x$gcc_cv_mips_explicit_relocs = x; then
gcc_cv_mips_explicit_relocs=no
if test x$gcc_cv_as != x; then
echo ' lw $4,%gp_rel(foo)($4)' > conftest.s
if $gcc_cv_as conftest.s -o conftest.o > /dev/null 2>&1; then
gcc_cv_mips_explicit_relocs=yes
fi
rm -f conftest.s conftest.o
fi
fi
if test $gcc_cv_mips_explicit_relocs = yes; then
test x$target_cpu_default != x || target_cpu_default=0
target_cpu_default="(${target_cpu_default}|MASK_EXPLICIT_RELOCS)"
fi
AC_MSG_RESULT($gcc_cv_mips_explicit_relocs)
;;
esac