make targetm.gen_ccmp{first,next} take rtx_insn **
gcc/ChangeLog: 2016-11-03 Trevor Saunders <tbsaunde+gcc@tbsaunde.org> * ccmp.c (expand_ccmp_expr_1): Adjust. (expand_ccmp_expr): Likewise. (expand_ccmp_next): Likewise. * config/aarch64/aarch64.c (aarch64_gen_ccmp_next): Likewise. (aarch64_gen_ccmp_first): Likewise. * doc/tm.texi: Regenerate. * target.def (gen_ccmp_first): Change argument types to rtx_insn *. (gen_ccmp_next): Likewise. From-SVN: r241811
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@ -1,3 +1,14 @@
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2016-11-03 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
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* ccmp.c (expand_ccmp_expr_1): Adjust.
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(expand_ccmp_expr): Likewise.
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(expand_ccmp_next): Likewise.
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* config/aarch64/aarch64.c (aarch64_gen_ccmp_next): Likewise.
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(aarch64_gen_ccmp_first): Likewise.
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* doc/tm.texi: Regenerate.
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* target.def (gen_ccmp_first): Change argument types to rtx_insn *.
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(gen_ccmp_next): Likewise.
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2016-11-03 Bin Cheng <bin.cheng@arm.com>
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* tree-vect-loop.c (destroy_loop_vec_info): Handle cond_expr.
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21
gcc/ccmp.c
21
gcc/ccmp.c
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@ -122,7 +122,7 @@ ccmp_candidate_p (gimple *g)
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GEN_SEQ returns all compare insns. */
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static rtx
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expand_ccmp_next (gimple *g, tree_code code, rtx prev,
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rtx *prep_seq, rtx *gen_seq)
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rtx_insn **prep_seq, rtx_insn **gen_seq)
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{
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rtx_code rcode;
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int unsignedp = TYPE_UNSIGNED (TREE_TYPE (gimple_assign_rhs1 (g)));
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@ -149,10 +149,8 @@ expand_ccmp_next (gimple *g, tree_code code, rtx prev,
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PREP_SEQ returns all insns to prepare opearand.
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GEN_SEQ returns all compare insns. */
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static rtx
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expand_ccmp_expr_1 (gimple *g, rtx *prep_seq, rtx *gen_seq)
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expand_ccmp_expr_1 (gimple *g, rtx_insn **prep_seq, rtx_insn **gen_seq)
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{
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rtx prep_seq_1, gen_seq_1;
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rtx prep_seq_2, gen_seq_2;
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tree exp = gimple_assign_rhs_to_tree (g);
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tree_code code = TREE_CODE (exp);
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gimple *gs0 = get_gimple_for_ssa_name (TREE_OPERAND (exp, 0));
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@ -180,6 +178,7 @@ expand_ccmp_expr_1 (gimple *g, rtx *prep_seq, rtx *gen_seq)
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rcode0 = get_rtx_code (code0, unsignedp0);
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rcode1 = get_rtx_code (code1, unsignedp1);
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rtx_insn *prep_seq_1, *gen_seq_1;
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tmp = targetm.gen_ccmp_first (&prep_seq_1, &gen_seq_1, rcode0,
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gimple_assign_rhs1 (gs0),
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gimple_assign_rhs2 (gs0));
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@ -187,14 +186,15 @@ expand_ccmp_expr_1 (gimple *g, rtx *prep_seq, rtx *gen_seq)
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if (tmp != NULL)
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{
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ret = expand_ccmp_next (gs1, code, tmp, &prep_seq_1, &gen_seq_1);
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cost1 = seq_cost (safe_as_a <rtx_insn *> (prep_seq_1), speed_p);
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cost1 += seq_cost (safe_as_a <rtx_insn *> (gen_seq_1), speed_p);
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cost1 = seq_cost (prep_seq_1, speed_p);
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cost1 += seq_cost (gen_seq_1, speed_p);
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}
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/* FIXME: Temporary workaround for PR69619.
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Avoid exponential compile time due to expanding gs0 and gs1 twice.
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If gs0 and gs1 are complex, the cost will be high, so avoid
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reevaluation if above an arbitrary threshold. */
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rtx_insn *prep_seq_2, *gen_seq_2;
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if (tmp == NULL || cost1 < COSTS_N_INSNS (25))
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tmp2 = targetm.gen_ccmp_first (&prep_seq_2, &gen_seq_2, rcode1,
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gimple_assign_rhs1 (gs1),
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@ -207,8 +207,8 @@ expand_ccmp_expr_1 (gimple *g, rtx *prep_seq, rtx *gen_seq)
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{
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ret2 = expand_ccmp_next (gs0, code, tmp2, &prep_seq_2,
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&gen_seq_2);
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cost2 = seq_cost (safe_as_a <rtx_insn *> (prep_seq_2), speed_p);
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cost2 += seq_cost (safe_as_a <rtx_insn *> (gen_seq_2), speed_p);
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cost2 = seq_cost (prep_seq_2, speed_p);
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cost2 += seq_cost (gen_seq_2, speed_p);
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}
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if (cost2 < cost1)
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@ -262,14 +262,13 @@ expand_ccmp_expr (gimple *g)
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{
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rtx_insn *last;
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rtx tmp;
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rtx prep_seq, gen_seq;
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prep_seq = gen_seq = NULL_RTX;
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if (!ccmp_candidate_p (g))
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return NULL_RTX;
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last = get_last_insn ();
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rtx_insn *prep_seq = NULL, *gen_seq = NULL;
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tmp = expand_ccmp_expr_1 (g, &prep_seq, &gen_seq);
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if (tmp)
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@ -13234,7 +13234,7 @@ aarch64_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
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}
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static rtx
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aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq,
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aarch64_gen_ccmp_first (rtx_insn **prep_seq, rtx_insn **gen_seq,
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int code, tree treeop0, tree treeop1)
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{
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machine_mode op_mode, cmp_mode, cc_mode = CCmode;
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@ -13308,8 +13308,8 @@ aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq,
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}
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static rtx
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aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code,
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tree treeop0, tree treeop1, int bit_code)
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aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev,
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int cmp_code, tree treeop0, tree treeop1, int bit_code)
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{
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rtx op0, op1, target;
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machine_mode op_mode, cmp_mode, cc_mode = CCmode;
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@ -13318,7 +13318,7 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code,
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struct expand_operand ops[6];
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int aarch64_cond;
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push_to_sequence ((rtx_insn*) *prep_seq);
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push_to_sequence (*prep_seq);
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expand_operands (treeop0, treeop1, NULL_RTX, &op0, &op1, EXPAND_NORMAL);
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op_mode = GET_MODE (op0);
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@ -13384,7 +13384,7 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code,
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create_fixed_operand (&ops[4], prev);
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create_fixed_operand (&ops[5], GEN_INT (aarch64_cond));
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push_to_sequence ((rtx_insn*) *gen_seq);
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push_to_sequence (*gen_seq);
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if (!maybe_expand_insn (icode, 6, ops))
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{
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end_sequence ();
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@ -11550,7 +11550,7 @@ This target hook is required only when the target has several different
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modes and they have different conditional execution capability, such as ARM.
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@end deftypefn
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@deftypefn {Target Hook} rtx TARGET_GEN_CCMP_FIRST (rtx *@var{prep_seq}, rtx *@var{gen_seq}, int @var{code}, tree @var{op0}, tree @var{op1})
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@deftypefn {Target Hook} rtx TARGET_GEN_CCMP_FIRST (rtx_insn **@var{prep_seq}, rtx_insn **@var{gen_seq}, int @var{code}, tree @var{op0}, tree @var{op1})
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This function prepares to emit a comparison insn for the first compare in a
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sequence of conditional comparisions. It returns an appropriate comparison
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with @code{CC} for passing to @code{gen_ccmp_next} or @code{cbranch_optab}.
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@var{code} is the @code{rtx_code} of the compare for @var{op0} and @var{op1}.
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@end deftypefn
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@deftypefn {Target Hook} rtx TARGET_GEN_CCMP_NEXT (rtx *@var{prep_seq}, rtx *@var{gen_seq}, rtx @var{prev}, int @var{cmp_code}, tree @var{op0}, tree @var{op1}, int @var{bit_code})
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@deftypefn {Target Hook} rtx TARGET_GEN_CCMP_NEXT (rtx_insn **@var{prep_seq}, rtx_insn **@var{gen_seq}, rtx @var{prev}, int @var{cmp_code}, tree @var{op0}, tree @var{op1}, int @var{bit_code})
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This function prepares to emit a conditional comparison within a sequence
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of conditional comparisons. It returns an appropriate comparison with
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@code{CC} for passing to @code{gen_ccmp_next} or @code{cbranch_optab}.
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@ -2627,7 +2627,7 @@ DEFHOOK
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insns are saved in @var{gen_seq}. They will be emitted when all the\n\
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compares in the the conditional comparision are generated without error.\n\
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@var{code} is the @code{rtx_code} of the compare for @var{op0} and @var{op1}.",
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rtx, (rtx *prep_seq, rtx *gen_seq, int code, tree op0, tree op1),
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rtx, (rtx_insn **prep_seq, rtx_insn **gen_seq, int code, tree op0, tree op1),
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NULL)
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DEFHOOK
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be appropriate for passing to @code{gen_ccmp_next} or @code{cbranch_optab}.\n\
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@var{code} is the @code{rtx_code} of the compare for @var{op0} and @var{op1}.\n\
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@var{bit_code} is @code{AND} or @code{IOR}, which is the op on the compares.",
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rtx, (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code, tree op0, tree op1, int bit_code),
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rtx, (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev, int cmp_code, tree op0, tree op1, int bit_code),
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NULL)
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/* Return a new value for loop unroll size. */
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