sh.c (reg_class_from_letter): Assign `k' to SIBCALL_REGS.
* config/sh/sh.c (reg_class_from_letter): Assign `k' to SIBCALL_REGS. (machine_dependent_reorg): Split all insns. * config/sh/sh.h (CONDITIONAL_REGISTER_USAGE): Compute reg_class_contents[SIBCALL_REGS]. (reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add SIBCALL_REGS. * config/sh/sh.md (calli_pcrel, call_pcrel, call_valuei_pcrel, call_value_pcrel, call, call_value, sibcall): Match even when not optimizing. (sibcalli_pcrel, sibcall_pcrel): Likewise. Use constraint `k' for call address. (sibcalli): Likewise. From-SVN: r37934
This commit is contained in:
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4d80892796
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cb51ecd2a5
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@ -1,3 +1,17 @@
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2000-12-01 Alexandre Oliva <aoliva@redhat.com>
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* config/sh/sh.c (reg_class_from_letter): Assign `k' to SIBCALL_REGS.
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(machine_dependent_reorg): Split all insns.
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* config/sh/sh.h (CONDITIONAL_REGISTER_USAGE): Compute
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reg_class_contents[SIBCALL_REGS].
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(reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add SIBCALL_REGS.
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* config/sh/sh.md (calli_pcrel, call_pcrel, call_valuei_pcrel,
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call_value_pcrel, call, call_value, sibcall): Match even when
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not optimizing.
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(sibcalli_pcrel, sibcall_pcrel): Likewise. Use constraint `k'
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for call address.
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(sibcalli): Likewise.
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2000-12-01 Joseph S. Myers <jsm28@cam.ac.uk>
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2000-12-01 Joseph S. Myers <jsm28@cam.ac.uk>
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* c-common.c (warn_format, warn_format_y2k,
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* c-common.c (warn_format, warn_format_y2k,
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@ -120,7 +120,7 @@ enum reg_class reg_class_from_letter[] =
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{
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{
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/* a */ ALL_REGS, /* b */ NO_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
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/* a */ ALL_REGS, /* b */ NO_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
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/* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
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/* e */ NO_REGS, /* f */ FP_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
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/* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ PR_REGS,
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/* i */ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
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/* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
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/* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
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/* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
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/* q */ NO_REGS, /* r */ NO_REGS, /* s */ NO_REGS, /* t */ T_REGS,
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/* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
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/* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
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@ -2913,6 +2913,12 @@ machine_dependent_reorg (first)
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rtx r0_rtx = gen_rtx_REG (Pmode, 0);
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rtx r0_rtx = gen_rtx_REG (Pmode, 0);
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rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
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rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
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/* We must split call insns before introducing `mova's. If we're
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optimizing, they'll have already been split. Otherwise, make
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sure we don't split them too late. */
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if (! optimize)
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split_all_insns (0);
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/* If relaxing, generate pseudo-ops to associate function calls with
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/* If relaxing, generate pseudo-ops to associate function calls with
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the symbols they call. It does no harm to not generate these
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the symbols they call. It does no harm to not generate these
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pseudo-ops. However, when we can generate them, it enables to
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pseudo-ops. However, when we can generate them, it enables to
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@ -63,17 +63,17 @@ extern int code_for_indirect_jump_scratch;
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/* We can not debug without a frame pointer. */
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/* We can not debug without a frame pointer. */
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/* #define CAN_DEBUG_WITHOUT_FP */
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/* #define CAN_DEBUG_WITHOUT_FP */
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#define CONDITIONAL_REGISTER_USAGE \
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#define CONDITIONAL_REGISTER_USAGE do \
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{ \
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int regno; \
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if (! TARGET_SH4 || ! TARGET_FMOVD) \
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if (! TARGET_SH4 || ! TARGET_FMOVD) \
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{ \
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{ \
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int regno; \
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for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++) \
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for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++) \
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fixed_regs[regno] = call_used_regs[regno] = 1; \
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fixed_regs[regno] = call_used_regs[regno] = 1; \
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if (! TARGET_SH4) \
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if (! TARGET_SH4) \
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{ \
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{ \
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if (! TARGET_SH3E) \
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if (! TARGET_SH3E) \
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{ \
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{ \
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int regno; \
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for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
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for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
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fixed_regs[regno] = call_used_regs[regno] = 1; \
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fixed_regs[regno] = call_used_regs[regno] = 1; \
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fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \
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fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \
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@ -87,7 +87,11 @@ extern int code_for_indirect_jump_scratch;
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{ \
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{ \
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call_used_regs[MACH_REG] = 0; \
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call_used_regs[MACH_REG] = 0; \
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call_used_regs[MACL_REG] = 0; \
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call_used_regs[MACL_REG] = 0; \
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}
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} \
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for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
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if (! fixed_regs[regno] && call_used_regs[regno]) \
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SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
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} while (0)
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/* ??? Need to write documentation for all SH options and add it to the
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/* ??? Need to write documentation for all SH options and add it to the
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invoke.texi file. */
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invoke.texi file. */
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@ -712,6 +716,7 @@ enum reg_class
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T_REGS,
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T_REGS,
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MAC_REGS,
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MAC_REGS,
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FPUL_REGS,
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FPUL_REGS,
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SIBCALL_REGS,
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GENERAL_REGS,
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GENERAL_REGS,
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FP0_REGS,
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FP0_REGS,
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FP_REGS,
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FP_REGS,
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@ -733,6 +738,7 @@ enum reg_class
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"T_REGS", \
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"T_REGS", \
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"MAC_REGS", \
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"MAC_REGS", \
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"FPUL_REGS", \
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"FPUL_REGS", \
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"SIBCALL_REGS", \
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"GENERAL_REGS", \
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"GENERAL_REGS", \
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"FP0_REGS", \
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"FP0_REGS", \
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"FP_REGS", \
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"FP_REGS", \
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@ -754,6 +760,8 @@ enum reg_class
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{ 0x00040000, 0x00000000 }, /* T_REGS */ \
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{ 0x00040000, 0x00000000 }, /* T_REGS */ \
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{ 0x00300000, 0x00000000 }, /* MAC_REGS */ \
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{ 0x00300000, 0x00000000 }, /* MAC_REGS */ \
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{ 0x00400000, 0x00000000 }, /* FPUL_REGS */ \
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{ 0x00400000, 0x00000000 }, /* FPUL_REGS */ \
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/* SIBCALL_REGS is initialized in CONDITIONAL_REGISTER_USAGE. */ \
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{ 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \
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{ 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS */ \
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{ 0x0081FFFF, 0x00000000 }, /* GENERAL_REGS */ \
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{ 0x01000000, 0x00000000 }, /* FP0_REGS */ \
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{ 0x01000000, 0x00000000 }, /* FP0_REGS */ \
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{ 0xFF000000, 0x000000FF }, /* FP_REGS */ \
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{ 0xFF000000, 0x000000FF }, /* FP_REGS */ \
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@ -3410,7 +3410,7 @@
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(use (reg:SI PIC_REG))
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(use (reg:SI PIC_REG))
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(clobber (reg:SI PR_REG))
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(clobber (reg:SI PR_REG))
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(clobber (match_scratch:SI 2 "=r"))]
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(clobber (match_scratch:SI 2 "=r"))]
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"TARGET_SH2 && optimize"
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"TARGET_SH2"
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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@ -3469,7 +3469,7 @@
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(use (reg:SI PIC_REG))
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(use (reg:SI PIC_REG))
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(clobber (reg:SI PR_REG))
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(clobber (reg:SI PR_REG))
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(clobber (match_scratch:SI 3 "=r"))]
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(clobber (match_scratch:SI 3 "=r"))]
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"TARGET_SH2 && optimize"
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"TARGET_SH2"
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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@ -3499,7 +3499,7 @@
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""
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""
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"
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"
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{
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{
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if (flag_pic && TARGET_SH2 && optimize
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if (flag_pic && TARGET_SH2
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&& GET_CODE (operands[0]) == MEM
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&& GET_CODE (operands[0]) == MEM
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&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
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&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
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{
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{
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@ -3519,7 +3519,7 @@
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""
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""
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"
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"
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{
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{
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if (flag_pic && TARGET_SH2 && optimize
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if (flag_pic && TARGET_SH2
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&& GET_CODE (operands[1]) == MEM
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&& GET_CODE (operands[1]) == MEM
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&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
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&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
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{
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{
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@ -3532,8 +3532,7 @@
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}")
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}")
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(define_insn "sibcalli"
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(define_insn "sibcalli"
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;; FIXME: any call-clobbered register will do
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[(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
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[(call (mem:SI (match_operand:SI 0 "register_operand" "z"))
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(match_operand 1 "" ""))
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(match_operand 1 "" ""))
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(use (reg:PSI FPSCR_REG))
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(use (reg:PSI FPSCR_REG))
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(return)]
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(return)]
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@ -3543,8 +3542,7 @@
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(set_attr "type" "jump_ind")])
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(set_attr "type" "jump_ind")])
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(define_insn "sibcalli_pcrel"
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(define_insn "sibcalli_pcrel"
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;; FIXME: any call-clobbered register will do
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[(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
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[(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "z"))
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(match_operand 1 "" ""))
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(match_operand 1 "" ""))
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(use (match_operand 2 "" ""))
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(use (match_operand 2 "" ""))
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(use (reg:PSI FPSCR_REG))
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(use (reg:PSI FPSCR_REG))
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@ -3558,10 +3556,9 @@
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[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
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[(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
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(match_operand 1 "" ""))
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(match_operand 1 "" ""))
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(use (reg:PSI FPSCR_REG))
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(use (reg:PSI FPSCR_REG))
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;; FIXME: any call-clobbered register will do
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(clobber (match_scratch:SI 2 "=k"))
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(clobber (match_scratch:SI 2 "=z"))
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(return)]
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(return)]
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"TARGET_SH2 && optimize"
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"TARGET_SH2"
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"#"
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"#"
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"reload_completed"
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"reload_completed"
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[(const_int 0)]
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[(const_int 0)]
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@ -3586,7 +3583,7 @@
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""
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""
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"
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"
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{
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{
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if (flag_pic && TARGET_SH2 && optimize
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if (flag_pic && TARGET_SH2
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&& GET_CODE (operands[0]) == MEM
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&& GET_CODE (operands[0]) == MEM
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&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
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&& GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
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/* The PLT needs the PIC register, but the epilogue would have
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/* The PLT needs the PIC register, but the epilogue would have
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