aarch64: Reimplement vaddlv* intrinsics using builtins
This patch reimplements the vaddlv* intrinsics using builtins. The vaddlv_s32 and vaddlv_u32 intrinsics actually perform a pairwise SADDLP/UADDLP instead of a SADDLV/UADDLV but because they only use two elements it has the same semantics. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (saddlv, uaddlv): Define builtins. * config/aarch64/aarch64-simd.md (aarch64_<su>addlv<mode>): Define. * config/aarch64/arm_neon.h (vaddlv_s8): Reimplement using builtin. (vaddlv_s16): Likewise. (vaddlv_u8): Likewise. (vaddlv_u16): Likewise. (vaddlvq_s8): Likewise. (vaddlvq_s16): Likewise. (vaddlvq_s32): Likewise. (vaddlvq_u8): Likewise. (vaddlvq_u16): Likewise. (vaddlvq_u32): Likewise. (vaddlv_s32): Likewise. (vaddlv_u32): Likewise. * config/aarch64/iterators.md (VDQV_L): New mode iterator. (unspec): Add UNSPEC_SADDLV, UNSPEC_UADDLV. (Vwstype): New mode attribute. (Vwsuf): Likewise. (VWIDE_S): Likewise. (USADDLV): New int iterator. (su): Handle UNSPEC_SADDLV, UNSPEC_UADDLV. gcc/testsuite/ChangeLog: * gcc.target/aarch64/simd/vaddlv_1.c: New test.
This commit is contained in:
Kyrylo Tkachov
parent
e053f96a9f
commit
cb995de62a
@ -149,6 +149,10 @@
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BUILTIN_VDQ_BHSI (BINOP, srhadd, 0, NONE)
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BUILTIN_VDQ_BHSI (BINOP, urhadd, 0, NONE)
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/* Implemented by aarch64_<su>addlv<mode>. */
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BUILTIN_VDQV_L (UNOP, saddlv, 0, NONE)
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BUILTIN_VDQV_L (UNOPU, uaddlv, 0, NONE)
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/* Implemented by aarch64_<su>abd<mode>. */
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BUILTIN_VDQ_BHSI (BINOP, sabd, 0, NONE)
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BUILTIN_VDQ_BHSI (BINOPU, uabd, 0, NONE)
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@ -2695,6 +2695,15 @@
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[(set_attr "type" "neon_reduc_add<q>")]
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)
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(define_insn "aarch64_<su>addlv<mode>"
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[(set (match_operand:<VWIDE_S> 0 "register_operand" "=w")
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(unspec:<VWIDE_S> [(match_operand:VDQV_L 1 "register_operand" "w")]
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USADDLV))]
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"TARGET_SIMD"
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"<su>addl<vp>\\t%<Vwstype>0<Vwsuf>, %1.<Vtype>"
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[(set_attr "type" "neon_reduc_add<q>")]
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)
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;; ADDV with result zero-extended to SI/DImode (for popcount).
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(define_insn "aarch64_zero_extend<GPI:mode>_reduc_plus_<VDQV_E:mode>"
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[(set (match_operand:GPI 0 "register_operand" "=w")
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@ -7077,120 +7077,70 @@ __extension__ extern __inline int16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlv_s8 (int8x8_t __a)
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{
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int16_t __result;
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__asm__ ("saddlv %h0,%1.8b"
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: "=w"(__result)
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: "w"(__a)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_saddlvv8qi (__a);
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}
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__extension__ extern __inline int32_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlv_s16 (int16x4_t __a)
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{
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int32_t __result;
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__asm__ ("saddlv %s0,%1.4h"
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: "=w"(__result)
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: "w"(__a)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_saddlvv4hi (__a);
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}
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__extension__ extern __inline uint16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlv_u8 (uint8x8_t __a)
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{
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uint16_t __result;
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__asm__ ("uaddlv %h0,%1.8b"
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: "=w"(__result)
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: "w"(__a)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uaddlvv8qi_uu (__a);
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}
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__extension__ extern __inline uint32_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlv_u16 (uint16x4_t __a)
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{
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uint32_t __result;
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__asm__ ("uaddlv %s0,%1.4h"
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: "=w"(__result)
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: "w"(__a)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uaddlvv4hi_uu (__a);
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}
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__extension__ extern __inline int16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlvq_s8 (int8x16_t __a)
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{
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int16_t __result;
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__asm__ ("saddlv %h0,%1.16b"
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: "=w"(__result)
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: "w"(__a)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_saddlvv16qi (__a);
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}
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__extension__ extern __inline int32_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlvq_s16 (int16x8_t __a)
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{
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int32_t __result;
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__asm__ ("saddlv %s0,%1.8h"
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: "=w"(__result)
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: "w"(__a)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_saddlvv8hi (__a);
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}
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__extension__ extern __inline int64_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlvq_s32 (int32x4_t __a)
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{
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int64_t __result;
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__asm__ ("saddlv %d0,%1.4s"
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: "=w"(__result)
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: "w"(__a)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_saddlvv4si (__a);
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}
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__extension__ extern __inline uint16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlvq_u8 (uint8x16_t __a)
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{
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uint16_t __result;
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__asm__ ("uaddlv %h0,%1.16b"
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: "=w"(__result)
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: "w"(__a)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uaddlvv16qi_uu (__a);
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}
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__extension__ extern __inline uint32_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlvq_u16 (uint16x8_t __a)
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{
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uint32_t __result;
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__asm__ ("uaddlv %s0,%1.8h"
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: "=w"(__result)
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: "w"(__a)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uaddlvv8hi_uu (__a);
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}
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__extension__ extern __inline uint64_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlvq_u32 (uint32x4_t __a)
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{
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uint64_t __result;
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__asm__ ("uaddlv %d0,%1.4s"
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: "=w"(__result)
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: "w"(__a)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uaddlvv4si_uu (__a);
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}
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__extension__ extern __inline float32x2_t
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@ -10281,18 +10231,14 @@ __extension__ extern __inline int64_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlv_s32 (int32x2_t __a)
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{
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int64_t __result;
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__asm__ ("saddlp %0.1d, %1.2s" : "=w"(__result) : "w"(__a) : );
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return __result;
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return __builtin_aarch64_saddlvv2si (__a);
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}
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__extension__ extern __inline uint64_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vaddlv_u32 (uint32x2_t __a)
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{
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uint64_t __result;
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__asm__ ("uaddlp %0.1d, %1.2s" : "=w"(__result) : "w"(__a) : );
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return __result;
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return __builtin_aarch64_uaddlvv2si_uu (__a);
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}
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__extension__ extern __inline int16x4_t
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@ -215,6 +215,9 @@
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;; Advanced SIMD modes for Integer reduction across lanes (zero/sign extended).
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(define_mode_iterator VDQV_E [V8QI V16QI V4HI V8HI])
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;; Advanced SIMD modes for Integer widening reduction across lanes.
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(define_mode_iterator VDQV_L [V8QI V16QI V4HI V8HI V4SI V2SI])
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;; All double integer narrow-able modes.
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(define_mode_iterator VDN [V4HI V2SI DI])
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@ -492,6 +495,8 @@
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UNSPEC_FMINV ; Used in aarch64-simd.md.
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UNSPEC_FADDV ; Used in aarch64-simd.md.
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UNSPEC_ADDV ; Used in aarch64-simd.md.
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UNSPEC_SADDLV ; Used in aarch64-simd.md.
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UNSPEC_UADDLV ; Used in aarch64-simd.md.
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UNSPEC_SMAXV ; Used in aarch64-simd.md.
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UNSPEC_SMINV ; Used in aarch64-simd.md.
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UNSPEC_UMAXV ; Used in aarch64-simd.md.
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@ -1303,6 +1308,20 @@
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(V8HI "4s") (V4SI "2d")
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(V8HF "4s") (V4SF "2d")])
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;; Widened scalar register suffixes.
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(define_mode_attr Vwstype [(V8QI "h") (V4HI "s")
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(V2SI "") (V16QI "h")
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(V8HI "s") (V4SI "d")])
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;; Add a .1d for V2SI.
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(define_mode_attr Vwsuf [(V8QI "") (V4HI "")
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(V2SI ".1d") (V16QI "")
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(V8HI "") (V4SI "")])
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;; Scalar mode of widened vector reduction.
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(define_mode_attr VWIDE_S [(V8QI "HI") (V4HI "SI")
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(V2SI "DI") (V16QI "HI")
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(V8HI "SI") (V4SI "DI")])
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;; Widened mode with half the element register suffixes for VD_BHSI/VQW/VQ_HSF.
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(define_mode_attr Vwhalf [(V8QI "4h") (V4HI "2s")
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(V2SI "1d") (V16QI "8h")
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@ -2184,6 +2203,8 @@
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(define_int_iterator SVE_INT_ADDV [UNSPEC_SADDV UNSPEC_UADDV])
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(define_int_iterator USADDLV [UNSPEC_SADDLV UNSPEC_UADDLV])
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(define_int_iterator LOGICALF [UNSPEC_ANDF UNSPEC_IORF UNSPEC_XORF])
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(define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
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@ -2934,6 +2955,8 @@
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;; "s" for signed operations and "u" for unsigned ones.
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(define_int_attr su [(UNSPEC_SADDV "s")
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(UNSPEC_UADDV "u")
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(UNSPEC_SADDLV "s")
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(UNSPEC_UADDLV "u")
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(UNSPEC_UNPACKSHI "s")
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(UNSPEC_UNPACKUHI "u")
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(UNSPEC_UNPACKSLO "s")
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56
gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c
Normal file
56
gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c
Normal file
@ -0,0 +1,56 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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#include <arm_neon.h>
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#define FUNC(IT, OT, S) \
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OT \
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foo_##S (IT a) \
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{ \
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return vaddlv_##S (a);\
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}
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FUNC (int8x8_t, int16_t, s8)
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/* { dg-final { scan-assembler-times {saddlv\th0, v0\.8b} 1} } */
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FUNC (int16x4_t, int32_t, s16)
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/* { dg-final { scan-assembler-times {saddlv\ts0, v0\.4h} 1} } */
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FUNC (int32x2_t, int64_t, s32)
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/* { dg-final { scan-assembler-times {saddlp\tv0\.1d, v0\.2s} 1} } */
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FUNC (uint8x8_t, uint16_t, u8)
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/* { dg-final { scan-assembler-times {uaddlv\th0, v0\.8b} 1} } */
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FUNC (uint16x4_t, uint32_t, u16)
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/* { dg-final { scan-assembler-times {uaddlv\ts0, v0\.4h} 1} } */
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FUNC (uint32x2_t, uint64_t, u32)
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/* { dg-final { scan-assembler-times {uaddlp\tv0.1d, v0\.2s} 1} } */
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#define FUNCQ(IT, OT, S) \
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OT \
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fooq_##S (IT a) \
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{ \
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return vaddlvq_##S (a); \
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}
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FUNCQ (int8x16_t, int16_t, s8)
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/* { dg-final { scan-assembler-times {saddlv\th0, v0\.16b} 1} } */
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FUNCQ (int16x8_t, int32_t, s16)
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/* { dg-final { scan-assembler-times {saddlv\ts0, v0\.8h} 1} } */
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FUNCQ (int32x4_t, int64_t, s32)
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/* { dg-final { scan-assembler-times {saddlv\td0, v0\.4s} 1} } */
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FUNCQ (uint8x16_t, uint16_t, u8)
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/* { dg-final { scan-assembler-times {uaddlv\th0, v0\.16b} 1} } */
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FUNCQ (uint16x8_t, uint32_t, u16)
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/* { dg-final { scan-assembler-times {uaddlv\ts0, v0\.8h} 1} } */
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FUNCQ (uint32x4_t, uint64_t, u32)
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/* { dg-final { scan-assembler-times {uaddlv\td0, v0\.4s} 1} } */
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