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arm: Set predicable on more instructions. 

Make sure its set for all CMP, CMN, TST instructions,
which do work inside IT blocks.

        * config/arm/arm.md (*addsi3_compare0_scratch): Set predicable.
        (*compare_negsi_si, *compare_addsi2_op0): Likewise.
        (*compare_addsi2_op1, *zeroextractsi_compare0_scratch): Likewise.
        (*compareqi_eq0, *arm_cmpsi_insn, *arm_cmpsi_negshiftsi_si): Likewise.

From-SVN: r182353
This commit is contained in:
Richard Henderson 2011-12-14 16:23:32 -08:00 committed by Richard Henderson
parent 6a473864bd
commit cc50a1e14e
2 changed files with 24 additions and 9 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2011-12-14 Richard Henderson <rth@redhat.com>
* config/arm/arm.md (*addsi3_compare0_scratch): Set predicable.
(*compare_negsi_si, *compare_addsi2_op0): Likewise.
(*compare_addsi2_op1, *zeroextractsi_compare0_scratch): Likewise.
(*compareqi_eq0, *arm_cmpsi_insn, *arm_cmpsi_negshiftsi_si): Likewise.
2011-12-14 Richard Guenther <rguenther@suse.de>
* tree-cfg.c (replace_uses_by): Fixup TREE_CONSTANT for

26
gcc/config/arm/arm.md
View File

@ -848,7 +848,8 @@
"@
cmn%?\\t%0, %1
cmp%?\\t%0, #%n1"
[(set_attr "conds" "set")]
[(set_attr "conds" "set")
(set_attr "predicable" "yes")]
)
(define_insn "*compare_negsi_si"
@ -858,7 +859,8 @@
(match_operand:SI 1 "s_register_operand" "r")))]
"TARGET_32BIT"
"cmn%?\\t%1, %0"
[(set_attr "conds" "set")]
[(set_attr "conds" "set")
(set_attr "predicable" "yes")]
)
;; This is the canonicalization of addsi3_compare0_for_combiner when the
@ -959,7 +961,8 @@
"@
cmn%?\\t%0, %1
cmp%?\\t%0, #%n1"
[(set_attr "conds" "set")]
[(set_attr "conds" "set")
(set_attr "predicable" "yes")]
)
(define_insn "*compare_addsi2_op1"
@ -972,7 +975,8 @@
"@
cmn%?\\t%0, %1
cmp%?\\t%0, #%n1"
[(set_attr "conds" "set")]
[(set_attr "conds" "set")
(set_attr "predicable" "yes")]
)
(define_insn "*addsi3_carryin_<optab>"
@ -2272,7 +2276,8 @@
output_asm_insn (\"tst%?\\t%0, %1\", operands);
return \"\";
"
[(set_attr "conds" "set")]
[(set_attr "conds" "set")
(set_attr "predicable" "yes")]
)
(define_insn_and_split "*ne_zeroextractsi"
@ -4713,8 +4718,9 @@
(compare:CC_Z (match_operand:QI 0 "s_register_operand" "r")
(const_int 0)))]
"TARGET_32BIT"
"tst\\t%0, #255"
[(set_attr "conds" "set")]
"tst%?\\t%0, #255"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")]
)
(define_expand "extendhisi2"
@ -7470,7 +7476,8 @@
cmn%?\\t%0, #%n1"
[(set_attr "conds" "set")
(set_attr "arch" "t2,t2,any,any")
(set_attr "length" "2,2,4,4")]
(set_attr "length" "2,2,4,4")
(set_attr "predicable" "yes")]
)
(define_insn "*cmpsi_shiftsi"
@ -7511,7 +7518,8 @@
[(set_attr "conds" "set")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
(const_string "alu_shift")
(const_string "alu_shift_reg")))]
(const_string "alu_shift_reg")))
(set_attr "predicable" "yes")]
)
;; DImode comparisons. The generic code generates branches that