arm: Set predicable on more instructions.
Make sure its set for all CMP, CMN, TST instructions, which do work inside IT blocks. * config/arm/arm.md (*addsi3_compare0_scratch): Set predicable. (*compare_negsi_si, *compare_addsi2_op0): Likewise. (*compare_addsi2_op1, *zeroextractsi_compare0_scratch): Likewise. (*compareqi_eq0, *arm_cmpsi_insn, *arm_cmpsi_negshiftsi_si): Likewise. From-SVN: r182353
This commit is contained in:
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cc50a1e14e
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@ -1,3 +1,10 @@
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2011-12-14 Richard Henderson <rth@redhat.com>
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* config/arm/arm.md (*addsi3_compare0_scratch): Set predicable.
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(*compare_negsi_si, *compare_addsi2_op0): Likewise.
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(*compare_addsi2_op1, *zeroextractsi_compare0_scratch): Likewise.
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(*compareqi_eq0, *arm_cmpsi_insn, *arm_cmpsi_negshiftsi_si): Likewise.
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2011-12-14 Richard Guenther <rguenther@suse.de>
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2011-12-14 Richard Guenther <rguenther@suse.de>
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* tree-cfg.c (replace_uses_by): Fixup TREE_CONSTANT for
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* tree-cfg.c (replace_uses_by): Fixup TREE_CONSTANT for
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@ -848,7 +848,8 @@
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"@
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"@
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cmn%?\\t%0, %1
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cmn%?\\t%0, %1
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cmp%?\\t%0, #%n1"
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cmp%?\\t%0, #%n1"
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[(set_attr "conds" "set")]
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[(set_attr "conds" "set")
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(set_attr "predicable" "yes")]
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)
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)
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(define_insn "*compare_negsi_si"
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(define_insn "*compare_negsi_si"
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@ -858,7 +859,8 @@
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(match_operand:SI 1 "s_register_operand" "r")))]
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(match_operand:SI 1 "s_register_operand" "r")))]
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"TARGET_32BIT"
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"TARGET_32BIT"
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"cmn%?\\t%1, %0"
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"cmn%?\\t%1, %0"
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[(set_attr "conds" "set")]
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[(set_attr "conds" "set")
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(set_attr "predicable" "yes")]
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)
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)
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;; This is the canonicalization of addsi3_compare0_for_combiner when the
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;; This is the canonicalization of addsi3_compare0_for_combiner when the
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@ -959,7 +961,8 @@
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"@
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"@
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cmn%?\\t%0, %1
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cmn%?\\t%0, %1
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cmp%?\\t%0, #%n1"
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cmp%?\\t%0, #%n1"
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[(set_attr "conds" "set")]
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[(set_attr "conds" "set")
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(set_attr "predicable" "yes")]
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)
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)
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(define_insn "*compare_addsi2_op1"
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(define_insn "*compare_addsi2_op1"
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@ -972,7 +975,8 @@
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"@
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"@
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cmn%?\\t%0, %1
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cmn%?\\t%0, %1
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cmp%?\\t%0, #%n1"
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cmp%?\\t%0, #%n1"
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[(set_attr "conds" "set")]
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[(set_attr "conds" "set")
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(set_attr "predicable" "yes")]
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)
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)
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(define_insn "*addsi3_carryin_<optab>"
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(define_insn "*addsi3_carryin_<optab>"
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@ -2272,7 +2276,8 @@
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output_asm_insn (\"tst%?\\t%0, %1\", operands);
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output_asm_insn (\"tst%?\\t%0, %1\", operands);
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return \"\";
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return \"\";
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"
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"
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[(set_attr "conds" "set")]
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[(set_attr "conds" "set")
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(set_attr "predicable" "yes")]
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)
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)
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(define_insn_and_split "*ne_zeroextractsi"
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(define_insn_and_split "*ne_zeroextractsi"
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@ -4713,8 +4718,9 @@
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(compare:CC_Z (match_operand:QI 0 "s_register_operand" "r")
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(compare:CC_Z (match_operand:QI 0 "s_register_operand" "r")
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(const_int 0)))]
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(const_int 0)))]
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"TARGET_32BIT"
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"TARGET_32BIT"
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"tst\\t%0, #255"
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"tst%?\\t%0, #255"
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[(set_attr "conds" "set")]
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[(set_attr "conds" "set")
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(set_attr "predicable" "yes")]
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)
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)
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(define_expand "extendhisi2"
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(define_expand "extendhisi2"
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@ -7470,7 +7476,8 @@
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cmn%?\\t%0, #%n1"
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cmn%?\\t%0, #%n1"
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[(set_attr "conds" "set")
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[(set_attr "conds" "set")
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(set_attr "arch" "t2,t2,any,any")
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(set_attr "arch" "t2,t2,any,any")
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(set_attr "length" "2,2,4,4")]
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(set_attr "length" "2,2,4,4")
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(set_attr "predicable" "yes")]
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)
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)
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(define_insn "*cmpsi_shiftsi"
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(define_insn "*cmpsi_shiftsi"
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@ -7511,7 +7518,8 @@
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[(set_attr "conds" "set")
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[(set_attr "conds" "set")
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(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
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(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
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(const_string "alu_shift")
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(const_string "alu_shift")
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(const_string "alu_shift_reg")))]
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(const_string "alu_shift_reg")))
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(set_attr "predicable" "yes")]
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)
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)
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;; DImode comparisons. The generic code generates branches that
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;; DImode comparisons. The generic code generates branches that
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