mn10300: Emit the movm stores in the correct order.
From-SVN: r168671
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Richard Henderson
Richard Henderson
parent
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commit
cc909bba64
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@ -1,5 +1,11 @@
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2011-01-11 Richard Henderson <rth@redhat.com>
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* config/mn10300/mn10300.c (mn10300_gen_multiple_store): Make static.
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Emit register stores with the same offsets as the hardware.
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(mn10300_store_multiple_operation): Don't check that the register
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save offsets are monotonic.
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* config/mn10300/mn10300-protos.h: Update.
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* config/mn10300/mn10300.h (ASM_PN_FORMAT): Delete.
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* config/mn10300/mn10300.h (INCOMING_RETURN_ADDR_RTX): Define
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@ -27,7 +27,6 @@
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extern rtx mn10300_legitimize_pic_address (rtx, rtx);
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extern int mn10300_legitimate_pic_operand_p (rtx);
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extern bool mn10300_function_value_regno_p (const unsigned int);
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extern void mn10300_gen_multiple_store (int);
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extern int mn10300_get_live_callee_saved_regs (void);
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extern bool mn10300_hard_regno_mode_ok (unsigned int, Mmode);
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extern bool mn10300_legitimate_constant_p (rtx);
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@ -689,51 +689,61 @@ F (rtx r)
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(const_int -N*4)))
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(reg:SI R1))) */
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void
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mn10300_gen_multiple_store (int mask)
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static void
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mn10300_gen_multiple_store (unsigned int mask)
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{
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if (mask != 0)
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/* The order in which registers are stored, from SP-4 through SP-N*4. */
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static const unsigned int store_order[8] = {
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/* e2, e3: never saved */
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FIRST_EXTENDED_REGNUM + 4,
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FIRST_EXTENDED_REGNUM + 5,
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FIRST_EXTENDED_REGNUM + 6,
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FIRST_EXTENDED_REGNUM + 7,
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/* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */
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FIRST_DATA_REGNUM + 2,
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FIRST_DATA_REGNUM + 3,
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FIRST_ADDRESS_REGNUM + 2,
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FIRST_ADDRESS_REGNUM + 3,
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/* d0, d1, a0, a1, mdr, lir, lar: never saved. */
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};
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rtx x, elts[9];
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unsigned int i;
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int count;
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if (mask == 0)
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return;
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for (i = count = 0; i < ARRAY_SIZE(store_order); ++i)
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{
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int i;
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int count;
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rtx par;
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int pari;
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unsigned regno = store_order[i];
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/* Count how many registers need to be saved. */
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count = 0;
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for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
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if ((mask & (1 << i)) != 0)
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count += 1;
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if (((mask >> regno) & 1) == 0)
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continue;
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/* We need one PARALLEL element to update the stack pointer and
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an additional element for each register that is stored. */
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par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
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++count;
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x = plus_constant (stack_pointer_rtx, count * -4);
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x = gen_frame_mem (SImode, x);
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x = gen_rtx_SET (VOIDmode, x, gen_rtx_REG (SImode, regno));
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elts[count] = F(x);
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/* Create the instruction that updates the stack pointer. */
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XVECEXP (par, 0, 0)
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= F (gen_rtx_SET (SImode,
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stack_pointer_rtx,
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gen_rtx_PLUS (SImode,
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stack_pointer_rtx,
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GEN_INT (-count * 4))));
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/* Create each store. */
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pari = 1;
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for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
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if ((mask & (1 << i)) != 0)
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{
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rtx address = gen_rtx_PLUS (SImode,
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stack_pointer_rtx,
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GEN_INT (-pari * 4));
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XVECEXP(par, 0, pari)
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= F (gen_rtx_SET (VOIDmode,
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gen_rtx_MEM (SImode, address),
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gen_rtx_REG (SImode, i)));
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pari += 1;
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}
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F (emit_insn (par));
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/* Remove the register from the mask so that... */
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mask &= ~(1u << regno);
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}
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/* ... we can make sure that we didn't try to use a register
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not listed in the store order. */
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gcc_assert (mask == 0);
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/* Create the instruction that updates the stack pointer. */
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x = plus_constant (stack_pointer_rtx, count * -4);
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x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
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elts[0] = F(x);
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/* We need one PARALLEL element to update the stack pointer and
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an additional element for each register that is stored. */
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x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (count + 1, elts));
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F (emit_insn (x));
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}
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void
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@ -1273,27 +1283,19 @@ mn10300_store_multiple_operation (rtx op,
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|| INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
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return 0;
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/* Now go through the rest of the vector elements. They must be
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ordered so that the first instruction stores the highest-numbered
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register to the highest stack slot and that subsequent instructions
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store a lower-numbered register to the slot below.
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LAST keeps track of the smallest-numbered register stored so far.
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MASK is the set of stored registers. */
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last = LAST_EXTENDED_REGNUM + 1;
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mask = 0;
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for (i = 1; i < count; i++)
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{
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/* Check that element i is a (set (mem M) R) and that R is valid. */
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/* Check that element i is a (set (mem M) R). */
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/* ??? Validate the register order a-la mn10300_gen_multiple_store.
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Remember: the ordering is *not* monotonic. */
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elt = XVECEXP (op, 0, i);
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if (GET_CODE (elt) != SET
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|| (! MEM_P (SET_DEST (elt)))
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|| (! REG_P (SET_SRC (elt)))
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|| REGNO (SET_SRC (elt)) >= last)
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|| (! REG_P (SET_SRC (elt))))
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return 0;
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/* R was OK, so provisionally add it to MASK. We return 0 in any
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case if the rest of the instruction has a flaw. */
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/* Remember which registers are to be saved. */
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last = REGNO (SET_SRC (elt));
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mask |= (1 << last);
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