rs6000: ws -> wa
"ws" is just "wa". * config/rs6000/constraints.md (define_register_constraint "ws"): Delete. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_ws. * config/rs6000/rs6000.md: Adjust. * config/rs6000/vsx.md: Adjust. * doc/md.texi (Machine Constraints): Adjust. From-SVN: r271916
This commit is contained in:
parent
208a040511
commit
cc998fd5f4
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@ -1,3 +1,15 @@
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2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/constraints.md (define_register_constraint "ws"):
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Delete.
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* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
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(rs6000_init_hard_regno_mode_ok): Adjust.
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* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
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RS6000_CONSTRAINT_ws.
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* config/rs6000/rs6000.md: Adjust.
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* config/rs6000/vsx.md: Adjust.
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* doc/md.texi (Machine Constraints): Adjust.
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2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/constraints.md (define_register_constraint "wv"):
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@ -82,9 +82,6 @@
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(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
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"General purpose register if 64-bit instructions are enabled or NO_REGS.")
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(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]"
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"VSX vector register to hold scalar double values or NO_REGS.")
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(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
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"FP or VSX register to perform float operations under -mvsx or NO_REGS.")
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@ -2514,7 +2514,6 @@ rs6000_debug_reg_global (void)
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"wp reg_class = %s\n"
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"wq reg_class = %s\n"
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"wr reg_class = %s\n"
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"ws reg_class = %s\n"
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"ww reg_class = %s\n"
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"wx reg_class = %s\n"
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"wA reg_class = %s\n"
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@ -2529,7 +2528,6 @@ rs6000_debug_reg_global (void)
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
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@ -3144,7 +3142,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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wf - Preferred register class for V4SFmode.
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wn - always NO_REGS.
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wr - GPR if 64-bit mode is permitted.
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ws - Register class to do ISA 2.06 DF operations.
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ww - Register class to do SF conversions in with VSX operations.
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wx - Float register if we can do 32-bit int stores. */
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@ -3159,7 +3156,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
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rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
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rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
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rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
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}
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/* Add conditional constraints based on various options, to allow us to
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@ -1262,7 +1262,6 @@ enum r6000_reg_class_enum {
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RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
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RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
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RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
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RS6000_CONSTRAINT_ws, /* VSX register for DF */
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RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
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RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
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RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
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@ -469,10 +469,10 @@
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(TD "wn")])
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; Definitions for 64-bit VSX
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(define_mode_attr f64_vsx [(DF "ws") (DD "wn")])
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(define_mode_attr f64_vsx [(DF "wa") (DD "wn")])
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; Definitions for 64-bit direct move
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(define_mode_attr f64_dm [(DF "ws") (DD "d")])
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(define_mode_attr f64_dm [(DF "wa") (DD "d")])
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; Definitions for 64-bit use of altivec registers
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(define_mode_attr f64_av [(DF "v") (DD "wn")])
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@ -526,12 +526,12 @@
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; ISA 2.06 (power7). This includes instructions that normally target DF mode,
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; but are used on SFmode, since internally SFmode values are kept in the DFmode
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; format.
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(define_mode_attr Fv [(SF "ww") (DF "ws") (DI "wa")])
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(define_mode_attr Fv [(SF "ww") (DF "wa") (DI "wa")])
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; SF/DF constraint for arithmetic on VSX registers. This is intended to be
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; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
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; instructions added in ISA 2.07 (power8)
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(define_mode_attr Fv2 [(SF "wa") (DF "ws") (DI "wa")])
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(define_mode_attr Fv2 [(SF "wa") (DF "wa") (DI "wa")])
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; Which isa is needed for those float instructions?
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(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
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@ -626,7 +626,7 @@
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(DI "Y")])
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(define_mode_attr rreg [(SF "f")
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(DF "ws")
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(DF "wa")
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(TF "f")
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(TD "f")
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(V4SF "wf")
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@ -4783,7 +4783,7 @@
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})
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(define_insn_and_split "*extendsfdf2_fpr"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wa,v")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,wa,?wa,wa,v")
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(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wa,Z,wY")))]
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"TARGET_HARD_FLOAT && !HONOR_SNANS (SFmode)"
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"@
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@ -4804,7 +4804,7 @@
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(set_attr "isa" "*,*,*,*,p8v,p8v,p9v")])
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(define_insn "*extendsfdf2_snan"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
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(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f,wa")))]
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"TARGET_HARD_FLOAT && HONOR_SNANS (SFmode)"
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"@
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@ -4821,7 +4821,7 @@
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(define_insn "*truncdfsf2_fpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa")
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(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
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(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,wa")))]
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"TARGET_HARD_FLOAT"
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"@
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frsp %0,%1
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;; since the friz instruction does not truncate the value if the floating
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;; point value is < LONG_MIN or > LONG_MAX.
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(define_insn "*friz"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
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(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,ws"))))]
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
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(float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d,wa"))))]
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"TARGET_HARD_FLOAT && TARGET_FPRND
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&& flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ"
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"@
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@ -6223,7 +6223,7 @@
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})
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(define_insn "floatdidf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
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(float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
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"TARGET_FCFID && TARGET_HARD_FLOAT"
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"@
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; hit. We will split after reload to avoid the trip through the GPRs
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(define_insn_and_split "*floatdidf2_mem"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
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(float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
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(clobber (match_scratch:DI 2 "=d,wa"))]
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"TARGET_HARD_FLOAT && TARGET_FCFID"
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@ -6257,7 +6257,7 @@
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"")
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(define_insn "*floatunsdidf2_fcfidu"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
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(unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d,wa")))]
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"TARGET_HARD_FLOAT && TARGET_FCFIDU"
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"@
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@ -6266,7 +6266,7 @@
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[(set_attr "type" "fp")])
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(define_insn_and_split "*floatunsdidf2_mem"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
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(unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
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(clobber (match_scratch:DI 2 "=d,wa"))]
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"TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
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@ -7855,7 +7855,7 @@
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(define_insn_and_split "extenddf<mode>2_vsx"
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[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d")
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(float_extend:IBM128
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(match_operand:DF 1 "nonimmediate_operand" "ws,m")))]
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(match_operand:DF 1 "nonimmediate_operand" "wa,m")))]
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"TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)"
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"#"
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"&& reload_completed"
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@ -115,7 +115,7 @@
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(V2DI "wd")
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(V2DF "wd")
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(DI "wa")
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(DF "ws")
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(DF "wa")
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(SF "ww")
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(TF "wp")
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(KF "wq")
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@ -127,7 +127,7 @@
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;; hold the data
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(define_mode_attr VSr2 [(V2DF "wd")
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(V4SF "wf")
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(DF "ws")
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(DF "wa")
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(SF "ww")
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(DI "wa")
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(KF "wq")
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@ -135,20 +135,20 @@
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(define_mode_attr VSr3 [(V2DF "wa")
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(V4SF "wa")
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(DF "ws")
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(DF "wa")
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(SF "ww")
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(DI "wa")
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(KF "wq")
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(TF "wp")])
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;; Map the register class for sp<->dp float conversions, destination
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(define_mode_attr VSr4 [(SF "ws")
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(define_mode_attr VSr4 [(SF "wa")
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(DF "f")
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(V2DF "wd")
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(V4SF "v")])
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;; Map the register class for sp<->dp float conversions, source
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(define_mode_attr VSr5 [(SF "ws")
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(define_mode_attr VSr5 [(SF "wa")
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(DF "f")
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(V2DF "v")
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(V4SF "wd")])
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@ -163,7 +163,7 @@
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(V2DI "wa")
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(V2DF "wa")
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(DI "wa")
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(DF "ws")
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(DF "wa")
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(SF "ww")
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(V1TI "wa")
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(TI "wa")
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@ -277,7 +277,7 @@
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;; Map register class for 64-bit element in 128-bit vector for normal register
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;; to register moves
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(define_mode_attr VS_64reg [(V2DF "ws")
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(define_mode_attr VS_64reg [(V2DF "wa")
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(V2DI "wa")])
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;; Iterators for loading constants with xxspltib
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@ -2199,7 +2199,7 @@
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;; xscvspdp, represent the scalar SF type as V4SF
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(define_insn "vsx_xscvspdp"
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[(set (match_operand:DF 0 "vsx_register_operand" "=ws")
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[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
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(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
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UNSPEC_VSX_CVSPDP))]
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"VECTOR_UNIT_VSX_P (V4SFmode)"
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@ -2237,14 +2237,14 @@
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;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs
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(define_insn "vsx_xscvdpspn"
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[(set (match_operand:V4SF 0 "vsx_register_operand" "=ww")
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(unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "ws")]
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(unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wa")]
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UNSPEC_VSX_CVDPSPN))]
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"TARGET_XSCVDPSPN"
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"xscvdpspn %x0,%x1"
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[(set_attr "type" "fp")])
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(define_insn "vsx_xscvspdpn"
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[(set (match_operand:DF 0 "vsx_register_operand" "=ws")
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[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
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(unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
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UNSPEC_VSX_CVSPDPN))]
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"TARGET_XSCVSPDPN"
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@ -2453,7 +2453,7 @@
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[(set_attr "type" "vecdouble")])
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(define_insn "vsx_xvcvsxwdp_df"
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[(set (match_operand:DF 0 "vsx_register_operand" "=ws")
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[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
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(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
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UNSPEC_VSX_CVSXWDP))]
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"TARGET_VSX"
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@ -2469,7 +2469,7 @@
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[(set_attr "type" "vecdouble")])
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(define_insn "vsx_xvcvuxwdp_df"
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[(set (match_operand:DF 0 "vsx_register_operand" "=ws")
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[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
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(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
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UNSPEC_VSX_CVUXWDP))]
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"TARGET_VSX"
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@ -3771,7 +3771,7 @@
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;; Optimize double d = (double) vec_extract (vi, <n>)
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;; Get the element into the top position and use XVCVSWDP/XVCVUWDP
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(define_insn_and_split "*vsx_extract_si_<uns>float_df"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=ws")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
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(any_float:DF
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(vec_select:SI
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(match_operand:V4SI 1 "gpc_reg_operand" "v")
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@ -3818,7 +3818,7 @@
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(match_operand:V4SI 1 "gpc_reg_operand" "v")
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(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n")]))))
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(clobber (match_scratch:V4SI 3 "=v"))
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(clobber (match_scratch:DF 4 "=ws"))]
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(clobber (match_scratch:DF 4 "=wa"))]
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"VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
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"#"
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"&& 1"
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@ -4350,7 +4350,7 @@
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;; to the top element of the V2DF array without doing an extract.
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(define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df_scalar"
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[(set (match_operand:DF 0 "vfloat_operand" "=&ws,&?ws,ws,?ws")
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[(set (match_operand:DF 0 "vfloat_operand" "=&wa,&?wa,wa,?wa")
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(vec_select:DF
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(VEC_reduc:V2DF
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(vec_concat:V2DF
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@ -3197,7 +3197,7 @@ Altivec vector register
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Any VSX register if the @option{-mvsx} option was used or NO_REGS.
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When using any of the register constraints (@code{wa}, @code{wd}, @code{wf},
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@code{wp}, @code{wq}, @code{ws}, or @code{ww})
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@code{wp}, @code{wq}, or @code{ww})
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that take VSX registers, you must use @code{%x<n>} in the template so
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that the correct register is used. Otherwise the register number
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output in the assembly file will be incorrect if an Altivec register
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@ -3266,9 +3266,6 @@ VSX register to use for IEEE 128-bit floating point, or NO_REGS.
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@item wr
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General purpose register if 64-bit instructions are enabled or NO_REGS.
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@item ws
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VSX vector register to hold scalar double values or NO_REGS.
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@item ww
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FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
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