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Properly handle AVX256 unaligned load and store

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PR target/59084
	* config/i386/i386.c (ix86_option_override_internal): Check
	X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL and
	X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL for
	MASK_AVX256_SPLIT_UNALIGNED_LOAD and
	MASK_AVX256_SPLIT_UNALIGNED_STORE.

	* config/i386/x86-tune.def (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL):
	Clear m_COREI7_AVX and update comments.
	(X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL): Likewise.

From-SVN: r204700
This commit is contained in:
H.J. Lu 2013-11-12 13:26:51 +00:00 committed by H.J. Lu
parent 732dad8f32
commit cd3c1b1c70
3 changed files with 20 additions and 7 deletions
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13
gcc/ChangeLog
View File

@ -1,3 +1,16 @@
2013-11-12 H.J. Lu <hongjiu.lu@intel.com>
PR target/59084
* config/i386/i386.c (ix86_option_override_internal): Check
X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL and
X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL for
MASK_AVX256_SPLIT_UNALIGNED_LOAD and
MASK_AVX256_SPLIT_UNALIGNED_STORE.
* config/i386/x86-tune.def (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL):
Clear m_COREI7_AVX and update comments.
(X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL): Likewise.
2013-11-12 Martin Jambor <mjambor@suse.cz>
PR rtl-optimization/10474

4
gcc/config/i386/i386.c
View File

@ -3974,10 +3974,10 @@ ix86_option_override_internal (bool main_args_p,
if (flag_expensive_optimizations
&& !(opts_set->x_target_flags & MASK_VZEROUPPER))
opts->x_target_flags |= MASK_VZEROUPPER;
if (!ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL]
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_LOAD))
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_LOAD;
if (!ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL]
if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL]
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_STORE))
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
/* Enable 128-bit AVX instruction generation

10
gcc/config/i386/x86-tune.def
View File

@ -376,15 +376,15 @@ DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
/* AVX instruction selection tuning (some of SSE flags affects AVX, too) */
/*****************************************************************************/
/* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL: if true, unaligned loads are
/* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL: if false, unaligned loads are
split. */
DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL, "256_unaligned_load_optimal",
~(m_COREI7 | m_GENERIC))
~(m_COREI7 | m_COREI7_AVX | m_GENERIC))
/* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL: if true, unaligned loads are
/* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL: if false, unaligned stores are
split. */
DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_load_optimal",
~(m_COREI7 | m_BDVER | m_GENERIC))
DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_store_optimal",
~(m_COREI7 | m_COREI7_AVX | m_BDVER | m_GENERIC))
/* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
the auto-vectorizer. */