Generation of adjusted ldp/stp for vector types
Introduce simple peephole2 optimization which substitutes a sequence of four consecutive load or store (LDR, STR) instructions with two load or store pair (LDP, STP) instructions for 2 element supported vector modes (V2SI, V2SF, V2DI, and V2DF). Generated load / store pair instruction offset is adjusted accordingly. Bootstrapped and tested on aarch64-none-linux-gnu. Example: $ cat stp_vec_v2sf.c typedef float __attribute__((vector_size(8))) vec; void store_adjusted(vec *out, vec x, vec y) { out[400] = x; out[401] = y; out[402] = y; out[403] = x; } Example compiled with: $ ./aarch64-none-linux-gnu-gcc -S -O2 stp_vec_v2sf.c -dp Before the patch: store_adjusted: str d0, [x0, 3200] // 9 [c=4 l=4] *aarch64_simd_movv2si/2 str d1, [x0, 3208] // 11 [c=4 l=4] *aarch64_simd_movv2si/2 str d1, [x0, 3216] // 13 [c=4 l=4] *aarch64_simd_movv2si/2 str d0, [x0, 3224] // 15 [c=4 l=4] *aarch64_simd_movv2si/2 ret // 26 [c=0 l=4] *do_return After the patch: store_adjusted: add x1, x0, 3200 // 27 [c=4 l=4] *adddi3_aarch64/0 stp d0, d1, [x1] // 28 [c=0 l=4] vec_store_pairv2siv2si stp d1, d0, [x1, 16] // 29 [c=0 l=4] vec_store_pairv2siv2si ret // 22 [c=0 l=4] *do_return gcc/ChangeLog: * config/aarch64/aarch64-ldpstp.md: Add two peepholes for adjusted vector V2SI, V2SF, V2DI, V2DF load pair and store pair modes. * config/aarch64/aarch64-protos.h (aarch64_gen_adjusted_ldpstp): Change mode parameter to machine_mode. (aarch64_operands_adjust_ok_for_ldpstp): Change mode parameter to machine_mode. * config/aarch64/aarch64.c (aarch64_operands_adjust_ok_for_ldpstp): Change mode parameter to machine_mode. (aarch64_gen_adjusted_ldpstp): Change mode parameter to machine_mode. * config/aarch64/iterators.md (VP_2E): New iterator for 2 element vectors. gcc/testsuite/ChangeLog: * gcc.target/aarch64/ldp_vec_v2sf.c: New test. * gcc.target/aarch64/ldp_vec_v2si.c: New test. * gcc.target/aarch64/stp_vec_v2df.c: New test. * gcc.target/aarch64/stp_vec_v2di.c: New test. * gcc.target/aarch64/stp_vec_v2sf.c: New test. * gcc.target/aarch64/stp_vec_v2si.c: New test.
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@ -294,3 +294,45 @@
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else
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FAIL;
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})
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(define_peephole2
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[(match_scratch:DI 8 "r")
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(set (match_operand:VP_2E 0 "memory_operand" "")
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(match_operand:VP_2E 1 "aarch64_reg_or_zero" ""))
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(set (match_operand:VP_2E 2 "memory_operand" "")
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(match_operand:VP_2E 3 "aarch64_reg_or_zero" ""))
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(set (match_operand:VP_2E 4 "memory_operand" "")
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(match_operand:VP_2E 5 "aarch64_reg_or_zero" ""))
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(set (match_operand:VP_2E 6 "memory_operand" "")
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(match_operand:VP_2E 7 "aarch64_reg_or_zero" ""))
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(match_dup 8)]
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"TARGET_SIMD
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&& aarch64_operands_adjust_ok_for_ldpstp (operands, false, <MODE>mode)"
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[(const_int 0)]
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{
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if (aarch64_gen_adjusted_ldpstp (operands, false, <MODE>mode, UNKNOWN))
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DONE;
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else
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FAIL;
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})
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(define_peephole2
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[(match_scratch:DI 8 "r")
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(set (match_operand:VP_2E 0 "register_operand" "")
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(match_operand:VP_2E 1 "memory_operand" ""))
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(set (match_operand:VP_2E 2 "register_operand" "")
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(match_operand:VP_2E 3 "memory_operand" ""))
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(set (match_operand:VP_2E 4 "register_operand" "")
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(match_operand:VP_2E 5 "memory_operand" ""))
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(set (match_operand:VP_2E 6 "register_operand" "")
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(match_operand:VP_2E 7 "memory_operand" ""))
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(match_dup 8)]
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"TARGET_SIMD
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&& aarch64_operands_adjust_ok_for_ldpstp (operands, true, <MODE>mode)"
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[(const_int 0)]
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{
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if (aarch64_gen_adjusted_ldpstp (operands, true, <MODE>mode, UNKNOWN))
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DONE;
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else
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FAIL;
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})
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@ -682,7 +682,7 @@ void aarch64_split_compare_and_swap (rtx op[]);
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void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
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bool aarch64_gen_adjusted_ldpstp (rtx *, bool, scalar_mode, RTX_CODE);
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bool aarch64_gen_adjusted_ldpstp (rtx *, bool, machine_mode, RTX_CODE);
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void aarch64_expand_sve_vec_cmp_int (rtx, rtx_code, rtx, rtx);
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bool aarch64_expand_sve_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
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@ -733,7 +733,7 @@ int aarch64_ccmp_mode_to_code (machine_mode mode);
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bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
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bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode);
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bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode);
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bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, machine_mode);
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void aarch64_swap_ldrstr_operands (rtx *, bool);
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extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
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@ -22158,7 +22158,7 @@ aarch64_ldrstr_offset_compare (const void *x, const void *y)
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bool
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aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
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scalar_mode mode)
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machine_mode mode)
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{
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const int num_insns = 4;
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enum reg_class rclass;
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@ -22235,7 +22235,7 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
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for (int i = 0; i < num_insns; i++)
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offvals[i] = INTVAL (offset[i]);
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msize = GET_MODE_SIZE (mode);
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msize = GET_MODE_SIZE (mode).to_constant ();
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/* Check if the offsets can be put in the right order to do a ldp/stp. */
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qsort (offvals, num_insns, sizeof (HOST_WIDE_INT),
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@ -22275,7 +22275,7 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
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bool
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aarch64_gen_adjusted_ldpstp (rtx *operands, bool load,
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scalar_mode mode, RTX_CODE code)
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machine_mode mode, RTX_CODE code)
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{
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rtx base, offset_1, offset_3, t1, t2;
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rtx mem_1, mem_2, mem_3, mem_4;
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@ -22314,7 +22314,7 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load,
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&& offset_3 != NULL_RTX);
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/* Adjust offset so it can fit in LDP/STP instruction. */
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msize = GET_MODE_SIZE (mode);
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msize = GET_MODE_SIZE (mode).to_constant();
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stp_off_upper_limit = msize * (0x40 - 1);
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stp_off_lower_limit = - msize * 0x40;
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@ -98,6 +98,9 @@
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;; Copy of the above.
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(define_mode_iterator DREG2 [V8QI V4HI V4HF V2SI V2SF DF])
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;; All modes suitable to store/load pair (2 elements) using STP/LDP.
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(define_mode_iterator VP_2E [V2SI V2SF V2DI V2DF])
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;; Advanced SIMD, 64-bit container, all integer modes.
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(define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
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@ -0,0 +1,14 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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typedef float __attribute__((vector_size(8))) vec;
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vec
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load_long(vec *v) {
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return v[110] + v[111] + v[112] + v[113];
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}
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/* { dg-final { scan-assembler {add\tx[0-9]+, x[0-9]+, 880} } } */
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/* { dg-final { scan-assembler {ldp\td[0-9]+, d[0-9]+, \[x[0-9]+\]} } } */
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/* { dg-final { scan-assembler {ldp\td[0-9]+, d[0-9]+, \[x[0-9]+, 16\]} } } */
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/* { dg-final { scan-assembler-not "ldr\t" } } */
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@ -0,0 +1,14 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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typedef int __attribute__((vector_size(8))) vec;
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vec
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load_long(vec *v) {
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return v[110] + v[111] + v[112] + v[113];
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}
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/* { dg-final { scan-assembler {add\tx[0-9]+, x[0-9]+, 880} } } */
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/* { dg-final { scan-assembler {ldp\td[0-9]+, d[0-9]+, \[x[0-9]+\]} } } */
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/* { dg-final { scan-assembler {ldp\td[0-9]+, d[0-9]+, \[x[0-9]+, 16\]} } } */
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/* { dg-final { scan-assembler-not "ldr\t" } } */
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@ -0,0 +1,18 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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typedef double __attribute__((vector_size(16))) vec;
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void
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store_adjusted(vec *out, vec x, vec y)
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{
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out[100] = x;
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out[101] = y;
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out[102] = y;
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out[103] = x;
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}
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/* { dg-final { scan-assembler {add\tx[0-9]+, x[0-9]+, 1600} } } */
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/* { dg-final { scan-assembler {stp\tq[0-9]+, q[0-9]+, \[x[0-9]+\]} } } */
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/* { dg-final { scan-assembler {stp\tq[0-9]+, q[0-9]+, \[x[0-9]+, 32\]} } } */
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/* { dg-final { scan-assembler-not "str\t" } } */
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@ -0,0 +1,18 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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typedef long long __attribute__((vector_size(16))) vec;
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void
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store_adjusted(vec *out, vec x, vec y)
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{
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out[100] = x;
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out[101] = y;
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out[102] = y;
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out[103] = x;
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}
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/* { dg-final { scan-assembler {add\tx[0-9]+, x[0-9]+, 1600} } } */
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/* { dg-final { scan-assembler {stp\tq[0-9]+, q[0-9]+, \[x[0-9]+\]} } } */
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/* { dg-final { scan-assembler {stp\tq[0-9]+, q[0-9]+, \[x[0-9]+, 32\]} } } */
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/* { dg-final { scan-assembler-not "str\t" } } */
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@ -0,0 +1,18 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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typedef float __attribute__((vector_size(8))) vec;
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void
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store_adjusted(vec *out, vec x, vec y)
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{
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out[400] = x;
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out[401] = y;
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out[402] = y;
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out[403] = x;
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}
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/* { dg-final { scan-assembler {add\tx[0-9]+, x[0-9]+, 3200} } } */
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/* { dg-final { scan-assembler {stp\td[0-9]+, d[0-9]+, \[x[0-9]+\]} } } */
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/* { dg-final { scan-assembler {stp\td[0-9]+, d[0-9]+, \[x[0-9]+, 16\]} } } */
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/* { dg-final { scan-assembler-not "str\t" } } */
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@ -0,0 +1,18 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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typedef int __attribute__((vector_size(8))) vec;
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void
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store_adjusted(vec *out, vec x, vec y)
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{
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out[400] = x;
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out[401] = y;
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out[402] = y;
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out[403] = x;
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}
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/* { dg-final { scan-assembler {add\tx[0-9]+, x[0-9]+, 3200} } } */
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/* { dg-final { scan-assembler {stp\td[0-9]+, d[0-9]+, \[x[0-9]+\]} } } */
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/* { dg-final { scan-assembler {stp\td[0-9]+, d[0-9]+, \[x[0-9]+, 16\]} } } */
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/* { dg-final { scan-assembler-not "str\t" } } */
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