OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

mips.h (TUNE_OCTEON): New macro.

Browse Source 
* config/mips/mips.h (TUNE_OCTEON): New macro.
	* config/mips/mips.c (mips_issue_rate): Return 2 for Octeon.
	(mips_multipass_dfa_lookahead): Return 2 for Octeon.
	* config/mips/octeon.md: New file.
	* config/mips/mips.md: Include octeon.md.  Restore
	semi-alphabetical order of include files.

From-SVN: r140521
This commit is contained in:
Adam Nemet 2008-09-21 06:15:52 +00:00 committed by Adam Nemet
parent 4881ceecf3
commit ce00be9ede
5 changed files with 104 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
gcc/ChangeLog
View File

@ -1,3 +1,12 @@
2008-09-20 Adam Nemet <anemet@caviumnetworks.com>
* config/mips/mips.h (TUNE_OCTEON): New macro.
* config/mips/mips.c (mips_issue_rate): Return 2 for Octeon.
(mips_multipass_dfa_lookahead): Return 2 for Octeon.
* config/mips/octeon.md: New file.
* config/mips/mips.md: Include octeon.md. Restore
semi-alphabetical order of include files.
2008-09-20 H.J. Lu <hongjiu.lu@intel.com>
PR target/37571

4
gcc/config/mips/mips.c
View File

@ -10377,6 +10377,7 @@ mips_issue_rate (void)
case PROCESSOR_R5500:
case PROCESSOR_R7000:
case PROCESSOR_R9000:
case PROCESSOR_OCTEON:
return 2;
case PROCESSOR_SB1:
@ -10518,6 +10519,9 @@ mips_multipass_dfa_lookahead (void)
if (TUNE_LOONGSON_2EF)
return 4;
if (TUNE_OCTEON)
return 2;
return 0;
}

1
gcc/config/mips/mips.h
View File

@ -281,6 +281,7 @@ enum mips_code_readable_setting {
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
|| mips_tune == PROCESSOR_SB1A)

3
gcc/config/mips/mips.md
View File

@ -935,10 +935,11 @@
(include "6000.md")
(include "7000.md")
(include "9000.md")
(include "loongson2ef.md")
(include "octeon.md")
(include "sb1.md")
(include "sr71k.md")
(include "xlr.md")
(include "loongson2ef.md")
(include "generic.md")
;;

88
gcc/config/mips/octeon.md Normal file
View File

@ -0,0 +1,88 @@
;; Octeon pipeline description.
;; Copyright (C) 2008
;; Free Software Foundation, Inc.
;; This file is part of GCC.
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
;; Copyright (C) 2004, 2005, 2006 Cavium Networks.
;; Octeon is a dual-issue processor that can issue all instructions on
;; pipe0 and a subset on pipe1.
(define_automaton "octeon_main, octeon_mult")
(define_cpu_unit "octeon_pipe0" "octeon_main")
(define_cpu_unit "octeon_pipe1" "octeon_main")
(define_cpu_unit "octeon_mult" "octeon_mult")
(define_insn_reservation "octeon_arith" 1
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop"))
"octeon_pipe0 | octeon_pipe1")
(define_insn_reservation "octeon_condmove" 2
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "condmove"))
"octeon_pipe0 | octeon_pipe1")
(define_insn_reservation "octeon_load" 2
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "load,prefetch,mtc,mfc"))
"octeon_pipe0")
(define_insn_reservation "octeon_store" 1
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "store"))
"octeon_pipe0")
(define_insn_reservation "octeon_brj" 1
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "branch,jump,call,trap"))
"octeon_pipe0")
(define_insn_reservation "octeon_imul3" 5
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "imul3,pop,clz"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult")
(define_insn_reservation "octeon_imul" 2
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "imul,mthilo"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult")
(define_insn_reservation "octeon_mfhilo" 5
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "mfhilo"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult")
(define_insn_reservation "octeon_imadd" 4
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "imadd"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3")
(define_insn_reservation "octeon_idiv" 72
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "idiv"))
"(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71")
;; Assume both pipes are needed for unknown and multiple-instruction
;; patterns.
(define_insn_reservation "octeon_unknown" 1
(and (eq_attr "cpu" "octeon")
(eq_attr "type" "unknown,multi"))
"octeon_pipe0 + octeon_pipe1")