backport: re PR target/81833 (PowerPC: VSX: Miscompiles ffmpeg's scalarproduct_int16_vsx at -O1)
[gcc] 2017-09-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Backport from mainline 2017-09-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com> PR target/81833 * config/rs6000/altivec.md (altivec_vsum2sws): Convert from a define_insn to a define_expand. (altivec_vsum2sws_direct): New define_insn. (altivec_vsumsws): Convert from a define_insn to a define_expand. [gcc/testsuite] 2017-09-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Backport from mainline 2017-09-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com> PR target/81833 * gcc.target/powerpc/pr81833-1.c: New file. * gcc.target/powerpc/pr81833-2.c: New file. From-SVN: r252042
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Bill Schmidt
William Schmidt
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@ -1,3 +1,14 @@
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2017-09-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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Backport from mainline
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2017-09-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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PR target/81833
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* config/rs6000/altivec.md (altivec_vsum2sws): Convert from a
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define_insn to a define_expand.
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(altivec_vsum2sws_direct): New define_insn.
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(altivec_vsumsws): Convert from a define_insn to a define_expand.
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2017-09-11 Max Filippov <jcmvbkbc@gmail.com>
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Backport from mainline
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@ -1749,51 +1749,61 @@
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"vsum4s<VI_char>s %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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;; FIXME: For the following two patterns, the scratch should only be
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;; allocated for !VECTOR_ELT_ORDER_BIG, and the instructions should
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;; be emitted separately.
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(define_insn "altivec_vsum2sws"
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(define_expand "altivec_vsum2sws"
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[(use (match_operand:V4SI 0 "register_operand"))
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(use (match_operand:V4SI 1 "register_operand"))
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(use (match_operand:V4SI 2 "register_operand"))]
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"TARGET_ALTIVEC"
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{
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if (VECTOR_ELT_ORDER_BIG)
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emit_insn (gen_altivec_vsum2sws_direct (operands[0], operands[1],
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operands[2]));
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else
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{
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rtx tmp1 = gen_reg_rtx (V4SImode);
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rtx tmp2 = gen_reg_rtx (V4SImode);
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emit_insn (gen_altivec_vsldoi_v4si (tmp1, operands[2],
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operands[2], GEN_INT (12)));
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emit_insn (gen_altivec_vsum2sws_direct (tmp2, operands[1], tmp1));
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emit_insn (gen_altivec_vsldoi_v4si (operands[0], tmp2, tmp2,
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GEN_INT (4)));
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}
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DONE;
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})
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; FIXME: This can probably be expressed without an UNSPEC.
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(define_insn "altivec_vsum2sws_direct"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
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(match_operand:V4SI 2 "register_operand" "v")]
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UNSPEC_VSUM2SWS))
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
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(clobber (match_scratch:V4SI 3 "=v"))]
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
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"TARGET_ALTIVEC"
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"vsum2sws %0,%1,%2"
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[(set_attr "type" "veccomplex")])
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(define_expand "altivec_vsumsws"
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[(use (match_operand:V4SI 0 "register_operand"))
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(use (match_operand:V4SI 1 "register_operand"))
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(use (match_operand:V4SI 2 "register_operand"))]
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"TARGET_ALTIVEC"
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{
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if (VECTOR_ELT_ORDER_BIG)
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return "vsum2sws %0,%1,%2";
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emit_insn (gen_altivec_vsumsws_direct (operands[0], operands[1],
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operands[2]));
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else
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return "vsldoi %3,%2,%2,12\n\tvsum2sws %3,%1,%3\n\tvsldoi %0,%3,%3,4";
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}
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[(set_attr "type" "veccomplex")
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(set (attr "length")
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(if_then_else
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(match_test "VECTOR_ELT_ORDER_BIG")
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(const_string "4")
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(const_string "12")))])
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(define_insn "altivec_vsumsws"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
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(match_operand:V4SI 2 "register_operand" "v")]
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UNSPEC_VSUMSWS))
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(set (reg:SI VSCR_REGNO) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))
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(clobber (match_scratch:V4SI 3 "=v"))]
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"TARGET_ALTIVEC"
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{
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if (VECTOR_ELT_ORDER_BIG)
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return "vsumsws %0,%1,%2";
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else
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return "vspltw %3,%2,0\n\tvsumsws %3,%1,%3\n\tvsldoi %0,%3,%3,12";
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}
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[(set_attr "type" "veccomplex")
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(set (attr "length")
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(if_then_else
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(match_test "(VECTOR_ELT_ORDER_BIG)")
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(const_string "4")
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(const_string "12")))])
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{
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rtx tmp1 = gen_reg_rtx (V4SImode);
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rtx tmp2 = gen_reg_rtx (V4SImode);
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emit_insn (gen_altivec_vspltw_direct (tmp1, operands[2], const0_rtx));
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emit_insn (gen_altivec_vsumsws_direct (tmp2, operands[1], tmp1));
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emit_insn (gen_altivec_vsldoi_v4si (operands[0], tmp2, tmp2,
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GEN_INT (12)));
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}
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DONE;
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})
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; FIXME: This can probably be expressed without an UNSPEC.
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(define_insn "altivec_vsumsws_direct"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
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@ -1,3 +1,12 @@
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2017-09-12 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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Backport from mainline
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2017-09-05 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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PR target/81833
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* gcc.target/powerpc/pr81833-1.c: New file.
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* gcc.target/powerpc/pr81833-2.c: New file.
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2017-09-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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Backport from mainline
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59
gcc/testsuite/gcc.target/powerpc/pr81833-1.c
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59
gcc/testsuite/gcc.target/powerpc/pr81833-1.c
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@ -0,0 +1,59 @@
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/* PR81833: This used to fail due to improper implementation of vec_msum. */
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/* Test case relies on -mcpu=power7 or later. Currently we don't have
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machinery to express that, so we have two separate tests for -mcpu=power7
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and -mcpu=power8 to catch 32-bit BE on P7 and 64-bit BE/LE on P8. */
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/* { dg-do run } */
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/* { dg-require-effective-target p8vector_hw } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
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/* { dg-options "-mcpu=power8 -O2" } */
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#include <altivec.h>
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#define vec_u8 vector unsigned char
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#define vec_s8 vector signed char
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#define vec_u16 vector unsigned short
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#define vec_s16 vector signed short
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#define vec_u32 vector unsigned int
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#define vec_s32 vector signed int
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#define vec_f vector float
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#define LOAD_ZERO const vec_u8 zerov = vec_splat_u8 (0)
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#define zero_u8v (vec_u8) zerov
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#define zero_s8v (vec_s8) zerov
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#define zero_u16v (vec_u16) zerov
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#define zero_s16v (vec_s16) zerov
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#define zero_u32v (vec_u32) zerov
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#define zero_s32v (vec_s32) zerov
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signed int __attribute__((noinline))
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scalarproduct_int16_vsx (const signed short *v1, const signed short *v2,
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int order)
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{
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int i;
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LOAD_ZERO;
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register vec_s16 vec1;
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register vec_s32 res = vec_splat_s32 (0), t;
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signed int ires;
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for (i = 0; i < order; i += 8) {
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vec1 = vec_vsx_ld (0, v1);
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t = vec_msum (vec1, vec_vsx_ld (0, v2), zero_s32v);
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res = vec_sums (t, res);
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v1 += 8;
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v2 += 8;
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}
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res = vec_splat (res, 3);
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vec_ste (res, 0, &ires);
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return ires;
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}
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int main(void)
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{
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const signed short test_vec[] = { 1, 1, 1, 1, 1, 1, 1, 1 };
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if (scalarproduct_int16_vsx (test_vec, test_vec, 8) != 8)
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__builtin_abort ();
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return 0;
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}
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59
gcc/testsuite/gcc.target/powerpc/pr81833-2.c
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59
gcc/testsuite/gcc.target/powerpc/pr81833-2.c
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@ -0,0 +1,59 @@
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/* PR81833: This used to fail due to improper implementation of vec_msum. */
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/* Test case relies on -mcpu=power7 or later. Currently we don't have
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machinery to express that, so we have two separate tests for -mcpu=power7
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and -mcpu=power8 to catch 32-bit BE on P7 and 64-bit BE/LE on P8. */
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/* { dg-do run } */
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/* { dg-require-effective-target vsx_hw } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
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/* { dg-options "-mcpu=power7 -O2" } */
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#include <altivec.h>
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#define vec_u8 vector unsigned char
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#define vec_s8 vector signed char
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#define vec_u16 vector unsigned short
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#define vec_s16 vector signed short
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#define vec_u32 vector unsigned int
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#define vec_s32 vector signed int
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#define vec_f vector float
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#define LOAD_ZERO const vec_u8 zerov = vec_splat_u8 (0)
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#define zero_u8v (vec_u8) zerov
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#define zero_s8v (vec_s8) zerov
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#define zero_u16v (vec_u16) zerov
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#define zero_s16v (vec_s16) zerov
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#define zero_u32v (vec_u32) zerov
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#define zero_s32v (vec_s32) zerov
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signed int __attribute__((noinline))
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scalarproduct_int16_vsx (const signed short *v1, const signed short *v2,
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int order)
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{
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int i;
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LOAD_ZERO;
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register vec_s16 vec1;
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register vec_s32 res = vec_splat_s32 (0), t;
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signed int ires;
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for (i = 0; i < order; i += 8) {
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vec1 = vec_vsx_ld (0, v1);
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t = vec_msum (vec1, vec_vsx_ld (0, v2), zero_s32v);
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res = vec_sums (t, res);
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v1 += 8;
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v2 += 8;
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}
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res = vec_splat (res, 3);
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vec_ste (res, 0, &ires);
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return ires;
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}
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int main(void)
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{
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const signed short test_vec[] = { 1, 1, 1, 1, 1, 1, 1, 1 };
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if (scalarproduct_int16_vsx (test_vec, test_vec, 8) != 8)
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__builtin_abort ();
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return 0;
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}
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