tm.texi (Run-time Target): Add comment about flag_iso and strict ANSI.
2002-06-11 Eric Christopher <echristo@redhat.com> * doc/tm.texi (Run-time Target): Add comment about flag_iso and strict ANSI. * config/mips/ecoff.h (CPP_PREDEFINES): Remove. * config/mips/ecoffl.h: Ditto. * config/mips/elf64.h (SUBTARGET_CPP_SPEC): Remove. (CPP_PREDEFINES): Ditto. * config/mips/elfl64.h: Ditto. * config/mips/elfl.h: Ditto. * config/mips/iris3.h (CPP_PREDEFINES, SUBTARGET_CPP_SPEC): #if 0 out until irix header consolidation. * config/mips/iris5.h (CPP_PREDEFINES, SUBTARGET_CPP_SPEC): Replace with SUBTARGET_OS_CPP_BUILTINS. * config/mips/iris6.h: Ditto. (CPLUSPLUS_CPP_SPEC): Remove. * config/mips/linux.h: Ditto. * config/mips/netbsd.h: Ditto. * config/mips/openbsd.h: Ditto. * config/mips/rtems.h: Ditto. * config/mips/rtems64.h: Ditto. * config/mips/sni-svr4.h: Ditto. * config/mips/mips.h (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS32, ISA_MIPS64): New defines. (GENERATE_MULT3_SI, HAVE_SQRT_P, ISA_HAS_64BIT_REGS, ISA_HAS_BRANCHLIKELY, ISA_HAS_CONDMOVE, ISA_HAS_8CC, ISA_HAS_FP4, ISA_HAS_COND_TRAP, ISA_HAS_MADD_MSUB, ISA_HAS_NMADD_NMSUB, ISA_HAS_CLZ_CLO, ISA_HAS_DCLZ_DCLO): Use. (TARGET_CPU_CPP_BUILTINS): Define. (CPP_PREDEFINES, LONG_MAX_SPEC, CPP_FPR_SPEC, CPP_SPEC): Remove. * config/mips/mips.md (mulsi3_mult3): Use ISA_MIPS32/64. (movdicc): Remove check for ISA_MIPS32. (bunordered, bordered, bungt, bunlt, buneq, bunge, bunle, sunordered_df, sunordered_sf, sordered_df, sordered_sf, sunlt_df, sunlt_sf, sungt_df, sungt_sf, suneq_df, suneq_sf, sunge_df, sunge_sf, sunle_df, sunle_sf): New patterns. From-SVN: r54493
This commit is contained in:
parent
f5f35f6a37
commit
ce3649d27a
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@ -1,3 +1,40 @@
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2002-06-11 Eric Christopher <echristo@redhat.com>
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* doc/tm.texi (Run-time Target): Add comment about flag_iso
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and strict ANSI.
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* config/mips/ecoff.h (CPP_PREDEFINES): Remove.
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* config/mips/ecoffl.h: Ditto.
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* config/mips/elf64.h (SUBTARGET_CPP_SPEC): Remove.
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(CPP_PREDEFINES): Ditto.
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* config/mips/elfl64.h: Ditto.
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* config/mips/elfl.h: Ditto.
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* config/mips/iris3.h (CPP_PREDEFINES, SUBTARGET_CPP_SPEC): #if 0
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out until irix header consolidation.
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* config/mips/iris5.h (CPP_PREDEFINES, SUBTARGET_CPP_SPEC): Replace
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with SUBTARGET_OS_CPP_BUILTINS.
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* config/mips/iris6.h: Ditto.
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(CPLUSPLUS_CPP_SPEC): Remove.
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* config/mips/linux.h: Ditto.
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* config/mips/netbsd.h: Ditto.
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* config/mips/openbsd.h: Ditto.
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* config/mips/rtems.h: Ditto.
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* config/mips/rtems64.h: Ditto.
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* config/mips/sni-svr4.h: Ditto.
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* config/mips/mips.h (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4,
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ISA_MIPS32, ISA_MIPS64): New defines.
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(GENERATE_MULT3_SI, HAVE_SQRT_P, ISA_HAS_64BIT_REGS,
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ISA_HAS_BRANCHLIKELY, ISA_HAS_CONDMOVE, ISA_HAS_8CC, ISA_HAS_FP4,
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ISA_HAS_COND_TRAP, ISA_HAS_MADD_MSUB, ISA_HAS_NMADD_NMSUB,
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ISA_HAS_CLZ_CLO, ISA_HAS_DCLZ_DCLO): Use.
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(TARGET_CPU_CPP_BUILTINS): Define.
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(CPP_PREDEFINES, LONG_MAX_SPEC, CPP_FPR_SPEC, CPP_SPEC): Remove.
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* config/mips/mips.md (mulsi3_mult3): Use ISA_MIPS32/64.
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(movdicc): Remove check for ISA_MIPS32.
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(bunordered, bordered, bungt, bunlt, buneq, bunge, bunle,
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sunordered_df, sunordered_sf, sordered_df, sordered_sf,
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sunlt_df, sunlt_sf, sungt_df, sungt_sf, suneq_df, suneq_sf, sunge_df,
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sunge_sf, sunle_df, sunle_sf): New patterns.
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2002-06-11 Neil Booth <neil@daikokuya.demon.co.uk>
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* Makefile.in: Update cppmain.o.
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@ -24,9 +24,6 @@ Boston, MA 02111-1307, USA. */
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#include "mips/mips.h"
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR3000 -D_mips -D_MIPSEB -D_R3000"
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/* Use memcpy, et. al., rather than bcopy. */
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#define TARGET_MEM_FUNCTIONS
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@ -25,6 +25,3 @@ Boston, MA 02111-1307, USA. */
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#include "gofast.h"
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#include "mips/ecoff.h"
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000"
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@ -48,15 +48,6 @@ Boston, MA 02111-1307, USA. */
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#include "mips/mips.h"
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000"
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/* I would rather put this in CPP_PREDEFINES, but the gcc driver
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doesn't handle -U options in CPP_PREDEFINES. */
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#undef SUBTARGET_CPP_SPEC
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#define SUBTARGET_CPP_SPEC "\
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%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}}"
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/* Use memcpy, et. al., rather than bcopy. */
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#define TARGET_MEM_FUNCTIONS
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@ -24,6 +24,3 @@ Boston, MA 02111-1307, USA. */
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#define TARGET_ENDIAN_DEFAULT 0
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#include "mips/elf.h"
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000"
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@ -24,6 +24,3 @@ Boston, MA 02111-1307, USA. */
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#define TARGET_ENDIAN_DEFAULT 0
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#include "mips/elf64.h"
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR4000 -D_mips -D_MIPSEL -D_R4000"
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@ -21,16 +21,16 @@ Boston, MA 02111-1307, USA. */
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#define SGI_TARGET 1 /* inform other mips files this is SGI */
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/* Names to predefine in the preprocessor for this target machine. */
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/* Temporarily #if 0'd until Irix header consolidation. */
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#if 0
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#define CPP_PREDEFINES "\
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-Dunix -Dmips -Dsgi -DSVR3 -Dhost_mips -DMIPSEB -DSYSTYPE_SYSV \
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-Asystem=unix -Asystem=svr3 -Acpu=mips -Amachine=mips"
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#define STARTFILE_SPEC "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
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#define SUBTARGET_CPP_SPEC "\
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%{!ansi:-D__EXTENSIONS__} -D_MIPSEB -D_SYSTYPE_SYSV"
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#endif
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#define STARTFILE_SPEC "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
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#define LIB_SPEC \
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"%{!p:%{!pg:%{!static:%{!g*:-lc_s}} -lc}}%{p:-lc_p}%{pg:-lc_p} crtn.o%s"
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@ -62,30 +62,46 @@ Boston, MA 02111-1307, USA. */
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(DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
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|| !strcmp (STR, "rpath"))
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#define TARGET_OS_CPP_BUILTINS() \
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do { \
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builtin_define_std ("host_mips"); \
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builtin_define_std ("sgi"); \
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builtin_define_std ("unix"); \
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builtin_define_std ("SYSTYPE_SVR4"); \
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builtin_define ("_MODERN_C"); \
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builtin_define ("_SVR4_SOURCE"); \
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builtin_define ("__DSO__"); \
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builtin_define ("_MIPS_SIM=_MIPS_SIM_ABI32"); \
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builtin_define ("_MIPS_SZPTR=32"); \
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builtin_assert ("system=unix"); \
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builtin_assert ("system=svr4"); \
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builtin_assert ("machine=sgi"); \
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\
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if (!TARGET_FLOAT64) \
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builtin_define ("_MIPS_FPSET=16"); \
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else \
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builtin_define ("_MIPS_FPSET=32"); \
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\
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if (!TARGET_INT64) \
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builtin_define ("_MIPS_SZINT=32"); \
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else \
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builtin_define ("_MIPS_SZINT=64"); \
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\
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if (!TARGET_LONG64) \
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builtin_define ("_MIPS_SZLONG=32"); \
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else \
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builtin_define ("_MIPS_SZLONG=64"); \
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\
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if (!flag_iso) \
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{ \
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builtin_define ("__EXTENSIONS__"); \
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builtin_define ("_SGI_SOURCE"); \
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} \
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} while (0);
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#undef SUBTARGET_CC1_SPEC
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#define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}"
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/* ??? _MIPS_SIM and _MIPS_SZPTR should eventually depend on options when
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options for them exist. */
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES \
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"-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \
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-D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \
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-D_MIPS_SIM=_MIPS_SIM_ABI32 -D_MIPS_SZPTR=32 \
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-Asystem=unix -Asystem=svr4 -Acpu=mips -Amachine=sgi"
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#undef SUBTARGET_CPP_SPEC
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#define SUBTARGET_CPP_SPEC "\
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%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE -D_LONGLONG} \
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%{!mfp64: -D_MIPS_FPSET=16}%{mfp64: -D_MIPS_FPSET=32} \
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%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
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%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
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%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
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%{!mips1: %{!mips2: %{!mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS1}}} \
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%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \
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%{!mlong64: -D_MIPS_SZLONG=32}%{mlong64: -D_MIPS_SZLONG=64}"
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#undef LINK_SPEC
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#define LINK_SPEC "\
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%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
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@ -69,47 +69,75 @@ Boston, MA 02111-1307, USA. */
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system header files require it. This is OK, because gcc never warns
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when long long is used in system header files. Alternatively, we can
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add support for the SGI builtin type __long_long. */
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#undef CPP_PREDEFINES
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#define CPP_PREDEFINES \
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"-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \
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-D_LONGLONG -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \
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-Asystem=unix -Asystem=svr4 -Acpu=mips -Amachine=sgi"
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/* We must make -mips3 do what -mlong64 used to do. */
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/* ??? If no mipsX option given, but a mabi=X option is, then should set
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_MIPS_ISA based on the mabi=X option. */
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/* ??? If no mabi=X option give, but a mipsX option is, then should set
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_MIPS_SIM based on the mipsX option. */
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/* ??? Same for _MIPS_SZINT. */
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/* ??? Same for _MIPS_SZPTR. */
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#undef SUBTARGET_CPP_SPEC
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#define SUBTARGET_CPP_SPEC "\
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%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE} \
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%{mfp32: -D_MIPS_FPSET=16}%{!mfp32: -D_MIPS_FPSET=32} \
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%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
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%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
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%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
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%{mips4: -D_MIPS_ISA=_MIPS_ISA_MIPS4} \
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%{!mips*: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
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%{mabi=32: -D_MIPS_SIM=_MIPS_SIM_ABI32} \
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%{mabi=n32: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \
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%{mabi=64: -D_ABI64=3 -D_MIPS_SIM=_ABI64} \
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%{!mabi*: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \
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%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \
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%{mabi=32: -D_MIPS_SZLONG=32} \
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%{mabi=n32: -D_MIPS_SZLONG=32} \
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%{mabi=64: -D_MIPS_SZLONG=64} \
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%{!mabi*: -D_MIPS_SZLONG=32} \
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%{mabi=32: -D_MIPS_SZPTR=32} \
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%{mabi=n32: -D_MIPS_SZPTR=32} \
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%{mabi=64: -D_MIPS_SZPTR=64} \
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%{!mabi*: -D_MIPS_SZPTR=32} \
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%{!mips1:%{!mips2: -D_COMPILER_VERSION=601}} \
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%{!mips*: -U__mips -D__mips=3} \
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%{mabi=32: -U__mips64} \
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%{mabi=n32: -D__mips64} \
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%{mabi=64: -D__mips64} \
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%{!mabi*: -D__mips64}"
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/* The GNU C++ standard library requires that __EXTENSIONS__ and
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_SGI_SOURCE be defined on at least irix6.2 and probably all IRIX 6
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prior to 6.5. They normally get defined if !ansi, for g++ we want
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them regardless. We don't need this on IRIX 6.5 itself, but it
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shouldn't hurt other than the namespace pollution. */
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/* Undefine because this includes iris5.h. */
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#undef TARGET_OS_CPP_BUILTINS
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#define TARGET_OS_CPP_BUILTINS() \
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do { \
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builtin_define_std ("host_mips"); \
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builtin_define ("_LONGLONG"); \
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builtin_define ("_MODERN_C"); \
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builtin_define ("_SVR4_SOURCE"); \
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builtin_define_std ("SYSTYPE_SVR4"); \
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builtin_define ("__DSO__"); \
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builtin_define_std ("unix"); \
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builtin_define_std ("sgi"); \
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builtin_assert ("system=svr4"); \
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builtin_assert ("system=unix"); \
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builtin_assert ("machine=sgi"); \
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\
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if (mips_abi == ABI_32) \
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{ \
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builtin_define ("_MIPS_SIM=_MIPS_SIM_ABI32"); \
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builtin_define ("_MIPS_SZLONG=32"); \
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builtin_define ("_MIPS_SZPTR=32"); \
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} \
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else if (mips_abi == ABI_64) \
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{ \
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builtin_define ("_ABI64=3"); \
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builtin_define ("_MIPS_SIM=_ABI64"); \
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builtin_define ("_MIPS_SZLONG=64"); \
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builtin_define ("_MIPS_SZPTR=64"); \
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} \
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else \
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{ \
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builtin_define ("_ABIN32=2"); \
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builtin_define ("_MIPS_SIM=_ABIN32"); \
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builtin_define ("_MIPS_SZLONG=32"); \
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builtin_define ("_MIPS_SZPTR=32"); \
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} \
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\
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if (!TARGET_FLOAT64) \
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builtin_define ("_MIPS_FPSET=16"); \
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else \
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builtin_define ("_MIPS_FPSET=32"); \
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\
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if (!TARGET_INT64) \
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builtin_define ("_MIPS_SZINT=32"); \
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else \
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builtin_define ("_MIPS_SZINT=64"); \
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\
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if (!ISA_MIPS1 && !ISA_MIPS2) \
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builtin_define ("_COMPILER_VERSION=601"); \
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\
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if (c_language == clk_cplusplus) \
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{ \
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builtin_define ("__EXTENSIONS__"); \
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builtin_define ("_SGI_SOURCE"); \
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} \
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\
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if (!flag_iso) \
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{ \
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builtin_define ("__EXTENSIONS__"); \
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builtin_define ("_SGI_SOURCE"); \
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} \
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} while (0)
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/* The GNU C++ standard library requires that __EXTENSIONS__ and
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_SGI_SOURCE be defined on at least irix6.2 and probably all irix6
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@ -117,11 +145,6 @@ Boston, MA 02111-1307, USA. */
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!ansi, for g++ we want them regardless. We don't need this on
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irix6.5 itself, but it shouldn't hurt other than the namespace
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pollution. */
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#undef CPLUSPLUS_CPP_SPEC
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#define CPLUSPLUS_CPP_SPEC "\
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-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
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%{ansi:-D__EXTENSIONS__ -D_SGI_SOURCE} %(cpp) \
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"
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/* Irix 6 uses DWARF-2. */
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#define DWARF2_DEBUGGING_INFO
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|
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@ -127,67 +127,55 @@ void FN () \
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#undef TARGET_DEFAULT
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#define TARGET_DEFAULT (MASK_ABICALLS|MASK_GAS)
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/* Specify predefined symbols in preprocessor. */
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#undef CPP_PREDEFINES
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#if TARGET_ENDIAN_DEFAULT == 0
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#define CPP_PREDEFINES "-DMIPSEL -D_MIPSEL -Dunix -Dmips -D_mips \
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-DR3000 -D_R3000 -D__gnu_linux__ -Dlinux -Asystem=posix -Acpu=mips \
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-Amachine=mips -D__ELF__ -D__PIC__ -D__pic__"
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#else
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#define CPP_PREDEFINES "-DMIPSEB -D_MIPSEB -Dunix -Dmips -D_mips \
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||||
-DR3000 -D_R3000 -D__gnu_linux__ -Dlinux -Asystem=posix -Acpu=mips \
|
||||
-Amachine=mips -D__ELF__ -D__PIC__ -D__pic__"
|
||||
#endif
|
||||
#define TARGET_OS_CPP_BUILTINS() \
|
||||
do { \
|
||||
builtin_define ("__gnu_linux__"); \
|
||||
builtin_define ("__ELF__"); \
|
||||
builtin_define ("__PIC__"); \
|
||||
builtin_define ("__pic__"); \
|
||||
builtin_define_std ("unix"); \
|
||||
builtin_define_std ("linux"); \
|
||||
builtin_assert ("system=linux"); \
|
||||
/* The GNU C++ standard library requires this. */ \
|
||||
if (c_language = clk_cplusplus) \
|
||||
builtin_define ("_GNU_SOURCE"); \
|
||||
\
|
||||
if (mips_abi == ABI_N32) \
|
||||
{ \
|
||||
builtin_define ("_ABIN32=2"); \
|
||||
builtin_define ("_MIPS_SIM=_ABIN32"); \
|
||||
builtin_define ("_MIPS_SZLONG=32"); \
|
||||
builtin_define ("_MIPS_SZPTR=32"); \
|
||||
} \
|
||||
else if (mips_abi == ABI_64) \
|
||||
{ \
|
||||
builtin_define ("_ABI64=3"); \
|
||||
builtin_define ("_MIPS_SIM=_ABI64"); \
|
||||
builtin_define ("_MIPS_SZLONG=64"); \
|
||||
builtin_define ("_MIPS_SZPTR=64"); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
builtin_define ("_MIPS_SIM=_MIPS_SIM_ABI32"); \
|
||||
builtin_define ("_MIPS_SZLONG=32"); \
|
||||
builtin_define ("_MIPS_SZPTR=32"); \
|
||||
} \
|
||||
if (TARGET_FLOAT64) \
|
||||
builtin_define ("_MIPS_FPSET=32"); \
|
||||
else \
|
||||
builtin_define ("_MIPS_FPSET=16"); \
|
||||
\
|
||||
if (TARGET_INT64) \
|
||||
builtin_define ("_MIPS_SZINT=64"); \
|
||||
else \
|
||||
builtin_define ("_MIPS_SZINT=32"); \
|
||||
} while (0)
|
||||
|
||||
/* We must make -mips3 do what -mlong64 used to do. */
|
||||
/* ??? If no mipsX option given, but a mabi=X option is, then should set
|
||||
_MIPS_ISA based on the mabi=X option. */
|
||||
/* ??? If no mabi=X option give, but a mipsX option is, then should set
|
||||
_MIPS_SIM based on the mipsX option. */
|
||||
/* ??? Same for _MIPS_SZINT. */
|
||||
/* ??? Same for _MIPS_SZPTR. */
|
||||
#undef SUBTARGET_CPP_SPEC
|
||||
#define SUBTARGET_CPP_SPEC "\
|
||||
%{mfp32: -D_MIPS_FPSET=16} \
|
||||
%{mfp64: -D_MIPS_FPSET=32} \
|
||||
%{!mfp*: -D_MIPS_FPSET=32} \
|
||||
%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
|
||||
%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
|
||||
%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
|
||||
%{mips4: -D_MIPS_ISA=_MIPS_ISA_MIPS4} \
|
||||
%{mips5: -D_MIPS_ISA=_MIPS_ISA_MIPS5} \
|
||||
%{mips32: -D_MIPS_ISA=_MIPS_ISA_MIPS32} \
|
||||
%{mips64: -D_MIPS_ISA=_MIPS_ISA_MIPS64} \
|
||||
%{!mips*: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
|
||||
%{mabi=32: -D_MIPS_SIM=_MIPS_SIM_ABI32} \
|
||||
%{mabi=n32: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \
|
||||
%{mabi=64: -D_ABI64=3 -D_MIPS_SIM=_ABI64} \
|
||||
%{!mabi*: -D_MIPS_SIM=_MIPS_SIM_ABI32} \
|
||||
%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \
|
||||
%{mabi=32: -D_MIPS_SZLONG=32} \
|
||||
%{mabi=n32: -D_MIPS_SZLONG=32} \
|
||||
%{mabi=64: -D_MIPS_SZLONG=64} \
|
||||
%{!mabi*: -D_MIPS_SZLONG=32} \
|
||||
%{mabi=32: -D_MIPS_SZPTR=32} \
|
||||
%{mabi=n32: -D_MIPS_SZPTR=32} \
|
||||
%{mabi=64: -D_MIPS_SZPTR=64} \
|
||||
%{!mabi*: -D_MIPS_SZPTR=32} \
|
||||
%{!mips*: -U__mips -D__mips} \
|
||||
%{mabi=32: -U__mips64} \
|
||||
%{mabi=n32: -D__mips64} \
|
||||
%{mabi=64: -U__mips64} \
|
||||
%{!mabi*: -U__mips64} \
|
||||
%{fno-PIC:-U__PIC__ -U__pic__} %{fno-pic:-U__PIC__ -U__pic__} \
|
||||
%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} \
|
||||
%{pthread:-D_REENTRANT}"
|
||||
|
||||
/* The GNU C++ standard library requires that these macros be defined. */
|
||||
#undef CPLUSPLUS_CPP_SPEC
|
||||
#define CPLUSPLUS_CPP_SPEC "\
|
||||
-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
|
||||
-D_GNU_SOURCE %(cpp) \
|
||||
"
|
||||
|
||||
/* From iris5.h */
|
||||
/* -G is incompatible with -KPIC which is the default, so only allow objects
|
||||
in the small data section if the user explicitly asks for it. */
|
||||
|
|
|
@ -321,6 +321,14 @@ extern void sbss_section PARAMS ((void));
|
|||
/* Generate mips16 code */
|
||||
#define TARGET_MIPS16 (target_flags & MASK_MIPS16)
|
||||
|
||||
/* Generic ISA defines. */
|
||||
#define ISA_MIPS1 (mips_isa == 1)
|
||||
#define ISA_MIPS2 (mips_isa == 2)
|
||||
#define ISA_MIPS3 (mips_isa == 3)
|
||||
#define ISA_MIPS4 (mips_isa == 4)
|
||||
#define ISA_MIPS32 (mips_isa == 32)
|
||||
#define ISA_MIPS64 (mips_isa == 64)
|
||||
|
||||
/* Architecture target defines. */
|
||||
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
|
||||
#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
|
||||
|
@ -336,6 +344,126 @@ extern void sbss_section PARAMS ((void));
|
|||
#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
|
||||
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
|
||||
|
||||
/* Target CPU builtins. */
|
||||
#define TARGET_CPU_CPP_BUILTINS() \
|
||||
do \
|
||||
{ \
|
||||
builtin_assert ("cpu=mips"); \
|
||||
builtin_define ("__mips__"); \
|
||||
builtin_define ("_mips"); \
|
||||
\
|
||||
/* We do this here because __mips is defined below \
|
||||
and so we can't use builtin_define_std. */ \
|
||||
if (!flag_iso) \
|
||||
builtin_define ("mips"); \
|
||||
\
|
||||
if (TARGET_64BIT) \
|
||||
{ \
|
||||
builtin_define ("__mips64"); \
|
||||
/* Silly, but will do until processor defines. */ \
|
||||
builtin_define_std ("R4000"); \
|
||||
builtin_define ("_R4000"); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
/* Ditto. */ \
|
||||
builtin_define_std ("R3000"); \
|
||||
builtin_define ("_R3000"); \
|
||||
} \
|
||||
if (TARGET_FLOAT64) \
|
||||
builtin_define ("__mips_fpr=64"); \
|
||||
else \
|
||||
builtin_define ("__mips_fpr=32"); \
|
||||
\
|
||||
if (TARGET_MIPS16) \
|
||||
builtin_define ("__mips16"); \
|
||||
\
|
||||
if (ISA_MIPS1) \
|
||||
{ \
|
||||
builtin_define ("__mips=1"); \
|
||||
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
|
||||
} \
|
||||
else if (ISA_MIPS2) \
|
||||
{ \
|
||||
builtin_define ("__mips=2"); \
|
||||
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
|
||||
} \
|
||||
else if (ISA_MIPS3) \
|
||||
{ \
|
||||
builtin_define ("__mips=3"); \
|
||||
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
|
||||
} \
|
||||
else if (ISA_MIPS4) \
|
||||
{ \
|
||||
builtin_define ("__mips=4"); \
|
||||
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
|
||||
} \
|
||||
else if (ISA_MIPS32) \
|
||||
{ \
|
||||
builtin_define ("__mips=32"); \
|
||||
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
|
||||
} \
|
||||
else if (ISA_MIPS64) \
|
||||
{ \
|
||||
builtin_define ("__mips=64"); \
|
||||
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
|
||||
} \
|
||||
\
|
||||
if (TARGET_HARD_FLOAT) \
|
||||
builtin_define ("__mips_hard_float"); \
|
||||
else if (TARGET_SOFT_FLOAT) \
|
||||
builtin_define ("__mips_soft_float"); \
|
||||
\
|
||||
if (TARGET_SINGLE_FLOAT) \
|
||||
builtin_define ("__mips_single_float"); \
|
||||
\
|
||||
if (TARGET_LONG64) \
|
||||
builtin_define ("__LONG_MAX__=9223372036854775807L"); \
|
||||
\
|
||||
if (TARGET_BIG_ENDIAN) \
|
||||
{ \
|
||||
builtin_define_std ("MIPSEB"); \
|
||||
builtin_define ("_MIPSEB"); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
builtin_define_std ("MIPSEL"); \
|
||||
builtin_define ("_MIPSEL"); \
|
||||
} \
|
||||
\
|
||||
/* Macros dependent on the C dialect. */ \
|
||||
if (preprocessing_asm_p ()) \
|
||||
{ \
|
||||
builtin_define_std ("LANGUAGE_ASSEMBLY"); \
|
||||
builtin_define ("_LANGUAGE_ASSEMBLY"); \
|
||||
} \
|
||||
else if (c_language == clk_c) \
|
||||
{ \
|
||||
builtin_define_std ("LANGUAGE_C"); \
|
||||
builtin_define ("_LANGUAGE_C"); \
|
||||
} \
|
||||
else if (c_language == clk_cplusplus) \
|
||||
{ \
|
||||
builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
|
||||
builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
|
||||
builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
|
||||
} \
|
||||
else if (c_language == clk_objective_c) \
|
||||
{ \
|
||||
builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
|
||||
builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
|
||||
/* Bizzare, but needed at least for Irix. */ \
|
||||
builtin_define_std ("LANGUAGE_C"); \
|
||||
builtin_define ("_LANGUAGE_C"); \
|
||||
} \
|
||||
\
|
||||
if (mips_abi == ABI_EABI) \
|
||||
builtin_define ("__mips_eabi"); \
|
||||
\
|
||||
} while (0)
|
||||
|
||||
|
||||
|
||||
/* Macro to define tables used to set the flags.
|
||||
This is a list in braces of pairs in braces,
|
||||
each pair being { "NAME", VALUE }
|
||||
|
@ -585,8 +713,8 @@ extern void sbss_section PARAMS ((void));
|
|||
|
||||
/* Generate three-operand multiply instructions for SImode. */
|
||||
#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
|
||||
|| mips_isa == 32 \
|
||||
|| mips_isa == 64) \
|
||||
|| ISA_MIPS32 \
|
||||
|| ISA_MIPS64) \
|
||||
&& !TARGET_MIPS16)
|
||||
|
||||
/* Generate three-operand multiply instructions for DImode. */
|
||||
|
@ -597,23 +725,23 @@ extern void sbss_section PARAMS ((void));
|
|||
depending on the instruction set architecture level. */
|
||||
|
||||
#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
|
||||
#define HAVE_SQRT_P() (mips_isa != 1)
|
||||
#define HAVE_SQRT_P() (!ISA_MIPS1)
|
||||
|
||||
/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
|
||||
#define ISA_HAS_64BIT_REGS (mips_isa == 3 \
|
||||
|| mips_isa == 4 \
|
||||
|| mips_isa == 64)
|
||||
#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
|
||||
|| ISA_MIPS4 \
|
||||
|| ISA_MIPS64)
|
||||
|
||||
/* ISA has branch likely instructions (eg. mips2). */
|
||||
/* Disable branchlikely for tx39 until compare rewrite. They haven't
|
||||
been generated up to this point. */
|
||||
#define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
|
||||
#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
|
||||
&& !TARGET_MIPS16)
|
||||
|
||||
/* ISA has the conditional move instructions introduced in mips4. */
|
||||
#define ISA_HAS_CONDMOVE ((mips_isa == 4 \
|
||||
|| mips_isa == 32 \
|
||||
|| mips_isa == 64) \
|
||||
#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
|
||||
|| ISA_MIPS32 \
|
||||
|| ISA_MIPS64) \
|
||||
&& !TARGET_MIPS16)
|
||||
|
||||
/* ISA has just the integer condition move instructions (movn,movz) */
|
||||
|
@ -621,37 +749,37 @@ extern void sbss_section PARAMS ((void));
|
|||
|
||||
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
|
||||
branch on CC, and move (both FP and non-FP) on CC. */
|
||||
#define ISA_HAS_8CC (mips_isa == 4 \
|
||||
|| mips_isa == 32 \
|
||||
|| mips_isa == 64)
|
||||
#define ISA_HAS_8CC (ISA_MIPS4 \
|
||||
|| ISA_MIPS32 \
|
||||
|| ISA_MIPS64)
|
||||
|
||||
/* This is a catch all for the other new mips4 instructions: indexed load and
|
||||
indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
|
||||
and the FP recip and recip sqrt instructions */
|
||||
#define ISA_HAS_FP4 (mips_isa == 4 \
|
||||
#define ISA_HAS_FP4 (ISA_MIPS4 \
|
||||
&& !TARGET_MIPS16)
|
||||
|
||||
/* ISA has conditional trap instructions. */
|
||||
#define ISA_HAS_COND_TRAP (mips_isa >= 2 \
|
||||
#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
|
||||
&& !TARGET_MIPS16)
|
||||
|
||||
/* ISA has multiply-accumulate instructions, madd and msub. */
|
||||
#define ISA_HAS_MADD_MSUB ((mips_isa == 32 \
|
||||
|| mips_isa == 64 \
|
||||
#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
|
||||
|| ISA_MIPS64 \
|
||||
) && !TARGET_MIPS16)
|
||||
|
||||
/* ISA has nmadd and nmsub instructions. */
|
||||
#define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
|
||||
#define ISA_HAS_NMADD_NMSUB (ISA_MIPS4 \
|
||||
&& ! TARGET_MIPS16)
|
||||
|
||||
/* ISA has count leading zeroes/ones instruction (not implemented). */
|
||||
#define ISA_HAS_CLZ_CLO ((mips_isa == 32 \
|
||||
|| mips_isa == 64 \
|
||||
#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
|
||||
|| ISA_MIPS64 \
|
||||
) && !TARGET_MIPS16)
|
||||
|
||||
/* ISA has double-word count leading zeroes/ones instruction (not
|
||||
implemented). */
|
||||
#define ISA_HAS_DCLZ_DCLO (mips_isa == 64 \
|
||||
#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
|
||||
&& !TARGET_MIPS16)
|
||||
|
||||
/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
|
||||
|
@ -761,14 +889,6 @@ while (0)
|
|||
#endif
|
||||
|
||||
|
||||
/* Names to predefine in the preprocessor for this target machine. */
|
||||
|
||||
#ifndef CPP_PREDEFINES
|
||||
#define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
|
||||
-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
|
||||
-Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
|
||||
#endif
|
||||
|
||||
/* Assembler specs. */
|
||||
|
||||
/* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
|
||||
|
@ -954,119 +1074,13 @@ extern int mips_abi;
|
|||
|
||||
/* Preprocessor specs. */
|
||||
|
||||
/* Rules for SIZE_TYPE and PTRDIFF_TYPE are:
|
||||
|
||||
both gp64 and long64 (not the options, but the corresponding flags,
|
||||
so defaults came into play) are required in order to have `long' in
|
||||
SIZE_TYPE and PTRDIFF_TYPE.
|
||||
|
||||
on eabi, -mips1, -mips2 and -mips32 disable gp64, whereas mips3,
|
||||
-mips4, -mips5 and -mips64 enable it.
|
||||
|
||||
on other ABIs, -mips* options do not affect gp32/64, but the
|
||||
default ISA affects the default gp size.
|
||||
|
||||
-mgp32 disables gp64, whereas -mgp64 enables it.
|
||||
|
||||
on eabi, gp64 implies long64.
|
||||
|
||||
-mlong64, and -mabi=64 are the only other ways to enable long64.
|
||||
|
||||
*/
|
||||
|
||||
#if MIPS_ISA_DEFAULT != 3 && MIPS_ISA_DEFAULT != 4 && MIPS_ISA_DEFAULT != 5 && MIPS_ISA_DEFAULT != 64
|
||||
|
||||
/* 32-bit cases first. */
|
||||
|
||||
#if MIPS_ABI_DEFAULT == ABI_EABI
|
||||
#define LONG_MAX_SPEC "\
|
||||
%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
|
||||
%{!mlong64:\
|
||||
%{mabi=eabi|!mabi=*:\
|
||||
%{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
|
||||
%{mips3|mips4|mips5|mips64|mgp64: \
|
||||
-D__LONG_MAX__=9223372036854775807L}}}}}}}} \
|
||||
"
|
||||
#else /* ABI_DEFAULT != ABI_EABI */
|
||||
#define LONG_MAX_SPEC "\
|
||||
%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
|
||||
%{!mlong64:\
|
||||
%{mabi=eabi:\
|
||||
%{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
|
||||
%{mips3|mips4|mips5|mips64|mgp64: \
|
||||
-D__LONG_MAX__=9223372036854775807L}}}}}}}} \
|
||||
"
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
/* 64-bit default ISA. */
|
||||
#if MIPS_ABI_DEFAULT == ABI_EABI
|
||||
#define LONG_MAX_SPEC "\
|
||||
%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
|
||||
%{!mlong64:\
|
||||
%{mabi=eabi|!mabi=*:\
|
||||
%{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
|
||||
-D__LONG_MAX__=9223372036854775807L}}}}}}}\
|
||||
"
|
||||
#else /* ABI_DEFAULT != ABI_EABI */
|
||||
#define LONG_MAX_SPEC "\
|
||||
%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
|
||||
%{!mlong64:\
|
||||
%{mabi=eabi:\
|
||||
%{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
|
||||
-D__LONG_MAX__=9223372036854775807L}}}}}}}\
|
||||
"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
|
||||
overridden by subtargets. */
|
||||
#ifndef SUBTARGET_CPP_SPEC
|
||||
#define SUBTARGET_CPP_SPEC ""
|
||||
#endif
|
||||
|
||||
/* Define appropriate macros for fpr register size. */
|
||||
#ifndef CPP_FPR_SPEC
|
||||
#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_FLOAT64)
|
||||
#define CPP_FPR_SPEC "-D__mips_fpr=64"
|
||||
#else
|
||||
#define CPP_FPR_SPEC "-D__mips_fpr=32"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
|
||||
of the source file extension. */
|
||||
#undef CPLUSPLUS_CPP_SPEC
|
||||
#define CPLUSPLUS_CPP_SPEC "\
|
||||
-D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
|
||||
%(cpp) \
|
||||
"
|
||||
/* CPP_SPEC is the set of arguments to pass to the preprocessor. */
|
||||
|
||||
#ifndef CPP_SPEC
|
||||
#define CPP_SPEC "\
|
||||
%{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
|
||||
%{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
|
||||
%{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
|
||||
%(subtarget_cpp_size_spec) \
|
||||
%{mips3:-U__mips -D__mips=3 -D__mips64} \
|
||||
%{mips4:-U__mips -D__mips=4 -D__mips64} \
|
||||
%{mips32:-U__mips -D__mips=32} \
|
||||
%{mips64:-U__mips -D__mips=64 -D__mips64} \
|
||||
%{mgp32:-U__mips64} %{mgp64:-D__mips64} \
|
||||
%{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \
|
||||
%{msingle-float:%{!msoft-float:-D__mips_single_float}} \
|
||||
%{m4650:%{!msoft-float:-D__mips_single_float}} \
|
||||
%{msoft-float:-D__mips_soft_float} \
|
||||
%{mabi=eabi:-D__mips_eabi} \
|
||||
%{mips16:%{!mno-mips16:-D__mips16}} \
|
||||
%{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
|
||||
%{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
|
||||
%(long_max_spec) \
|
||||
%(subtarget_cpp_spec) "
|
||||
#endif
|
||||
#define CPP_SPEC "%(subtarget_cpp_spec)"
|
||||
|
||||
/* This macro defines names of additional specifications to put in the specs
|
||||
that can be used in various specifications like CC1_SPEC. Its definition
|
||||
|
@ -1082,8 +1096,6 @@ extern int mips_abi;
|
|||
{ "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
|
||||
{ "cc1_cpu_spec", CC1_CPU_SPEC}, \
|
||||
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
|
||||
{ "long_max_spec", LONG_MAX_SPEC }, \
|
||||
{ "cpp_fpr_spec", CPP_FPR_SPEC }, \
|
||||
{ "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
|
||||
{ "gas_asm_spec", GAS_ASM_SPEC }, \
|
||||
{ "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, \
|
||||
|
@ -2302,7 +2314,7 @@ extern enum reg_class mips_char_to_class[256];
|
|||
: current_function_outgoing_args_size)
|
||||
#endif
|
||||
|
||||
/* The return address for the current frame is in r31 is this is a leaf
|
||||
/* The return address for the current frame is in r31 if this is a leaf
|
||||
function. Otherwise, it is on the stack. It is at a variable offset
|
||||
from sp/fp/ap, so we define a fake hard register rap which is a
|
||||
poiner to the return address on the stack. This always gets eliminated
|
||||
|
|
|
@ -1793,8 +1793,8 @@
|
|||
if (which_alternative == 1)
|
||||
return \"mult\\t%1,%2\";
|
||||
if (TARGET_MAD
|
||||
|| mips_isa == 32
|
||||
|| mips_isa == 64)
|
||||
|| ISA_MIPS32
|
||||
|| ISA_MIPS64)
|
||||
return \"mul\\t%0,%1,%2\";
|
||||
return \"mult\\t%0,%1,%2\";
|
||||
}"
|
||||
|
@ -8055,6 +8055,118 @@ move\\t%0,%z4\\n\\
|
|||
(set_attr "mode" "none")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_expand "bunordered"
|
||||
[(set (pc)
|
||||
(if_then_else (unordered:CC (cc0)
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (operands[0]) /* avoid unused code warning */
|
||||
{
|
||||
gen_conditional_branch (operands, UNORDERED);
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_expand "bordered"
|
||||
[(set (pc)
|
||||
(if_then_else (ordered:CC (cc0)
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (operands[0]) /* avoid unused code warning */
|
||||
{
|
||||
gen_conditional_branch (operands, ORDERED);
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_expand "bungt"
|
||||
[(set (pc)
|
||||
(if_then_else (ungt:CC (cc0)
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (operands[0]) /* avoid unused code warning */
|
||||
{
|
||||
gen_conditional_branch (operands, UNGT);
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_expand "bunlt"
|
||||
[(set (pc)
|
||||
(if_then_else (unlt:CC (cc0)
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (operands[0]) /* avoid unused code warning */
|
||||
{
|
||||
gen_conditional_branch (operands, UNLT);
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_expand "buneq"
|
||||
[(set (pc)
|
||||
(if_then_else (uneq:CC (cc0)
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (operands[0]) /* avoid unused code warning */
|
||||
{
|
||||
gen_conditional_branch (operands, UNEQ);
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_expand "bunge"
|
||||
[(set (pc)
|
||||
(if_then_else (unge:CC (cc0)
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (operands[0]) /* avoid unused code warning */
|
||||
{
|
||||
gen_conditional_branch (operands, UNGE);
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_expand "bunle"
|
||||
[(set (pc)
|
||||
(if_then_else (unle:CC (cc0)
|
||||
(const_int 0))
|
||||
(label_ref (match_operand 0 "" ""))
|
||||
(pc)))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (operands[0]) /* avoid unused code warning */
|
||||
{
|
||||
gen_conditional_branch (operands, UNLE);
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
(define_expand "beq"
|
||||
[(set (pc)
|
||||
(if_then_else (eq:CC (cc0)
|
||||
|
@ -9111,6 +9223,90 @@ move\\t%0,%z4\\n\\
|
|||
;;
|
||||
;; ....................
|
||||
|
||||
(define_insn "sunordered_df"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(unordered:CC (match_operand:DF 1 "register_operand" "f")
|
||||
(match_operand:DF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.un.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sordered_df"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(ordered:CC (match_operand:DF 1 "register_operand" "f")
|
||||
(match_operand:DF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.or.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sungt_df"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(ungt:CC (match_operand:DF 1 "register_operand" "f")
|
||||
(match_operand:DF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.ugt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sunlt_df"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(unlt:CC (match_operand:DF 1 "register_operand" "f")
|
||||
(match_operand:DF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.ult.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "suneq_df"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(uneq:CC (match_operand:DF 1 "register_operand" "f")
|
||||
(match_operand:DF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.ueq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sunge_df"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(unge:CC (match_operand:DF 1 "register_operand" "f")
|
||||
(match_operand:DF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.uge.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sunle_df"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(unle:CC (match_operand:DF 1 "register_operand" "f")
|
||||
(match_operand:DF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.ule.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "seq_df"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(eq:CC (match_operand:DF 1 "register_operand" "f")
|
||||
|
@ -9171,6 +9367,90 @@ move\\t%0,%z4\\n\\
|
|||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sunordered_sf"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(unordered:CC (match_operand:SF 1 "register_operand" "f")
|
||||
(match_operand:SF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.un.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sordered_sf"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(ordered:CC (match_operand:SF 1 "register_operand" "f")
|
||||
(match_operand:SF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.or.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sungt_sf"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(ungt:CC (match_operand:SF 1 "register_operand" "f")
|
||||
(match_operand:SF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.ugt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sunlt_sf"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(unlt:CC (match_operand:SF 1 "register_operand" "f")
|
||||
(match_operand:SF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.ult.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "suneq_sf"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(uneq:CC (match_operand:SF 1 "register_operand" "f")
|
||||
(match_operand:SF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.ueq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sunge_sf"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(unge:CC (match_operand:SF 1 "register_operand" "f")
|
||||
(match_operand:SF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.uge.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "sunle_sf"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(unle:CC (match_operand:SF 1 "register_operand" "f")
|
||||
(match_operand:SF 2 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"*
|
||||
{
|
||||
return mips_fill_delay_slot (\"c.ule.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
|
||||
}"
|
||||
[(set_attr "type" "fcmp")
|
||||
(set_attr "mode" "FPSW")])
|
||||
|
||||
(define_insn "seq_sf"
|
||||
[(set (match_operand:CC 0 "register_operand" "=z")
|
||||
(eq:CC (match_operand:SF 1 "register_operand" "f")
|
||||
|
@ -10529,8 +10809,6 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
|||
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
|
||||
"
|
||||
{
|
||||
if (mips_isa == 32)
|
||||
FAIL;
|
||||
gen_conditional_move (operands);
|
||||
DONE;
|
||||
}")
|
||||
|
|
|
@ -41,7 +41,6 @@ Boston, MA 02111-1307, USA. */
|
|||
{ \
|
||||
NETBSD_OS_CPP_BUILTINS_ELF(); \
|
||||
builtin_define ("__NO_LEADING_UNDERSCORES__"); \
|
||||
builtin_define ("__mips__"); \
|
||||
builtin_define ("__GP_SUPPORT__"); \
|
||||
builtin_assert ("machine=mips"); \
|
||||
if (TARGET_LONG64) \
|
||||
|
@ -67,7 +66,6 @@ Boston, MA 02111-1307, USA. */
|
|||
#undef US_SOFTWARE_GOFAST
|
||||
#undef INIT_SUBTARGET_OPTABS
|
||||
#define INIT_SUBTARGET_OPTABS
|
||||
#undef CPP_PREDEFINES
|
||||
|
||||
|
||||
/* Get generic NetBSD definitions. */
|
||||
|
@ -78,42 +76,6 @@ Boston, MA 02111-1307, USA. */
|
|||
#include <netbsd-elf.h>
|
||||
|
||||
|
||||
/* Provide a CPP_SPEC appropriate for NetBSD. This is a simplified
|
||||
CPP_SPEC from <mips/mips.h>. We (mostly) use the SUBTARGET_CPP_SPEC
|
||||
to deal with NetBSD-specific CPP options.
|
||||
|
||||
We default to MIPS-I at the very beginning of the spec, and let the
|
||||
value get overridden later, as necessary. We also set up a default
|
||||
endian spec.
|
||||
|
||||
This will get cleaned up once the MIPS target uses
|
||||
TARGET_CPU_CPP_BUILTINS(). */
|
||||
|
||||
#undef CPP_SPEC
|
||||
#define CPP_SPEC \
|
||||
"-D__mips=1 \
|
||||
%(subtarget_cpp_size_spec) \
|
||||
%{mips3:-U__mips -D__mips=3 -D__mips64} \
|
||||
%{mips4:-U__mips -D__mips=4 -D__mips64} \
|
||||
%{mips32:-U__mips -D__mips=32} \
|
||||
%{mips64:-U__mips -D__mips=64 -D__mips64} \
|
||||
%{mgp32:-U__mips64} %{mgp64:-D__mips64} \
|
||||
%{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} \
|
||||
%{!mfp32: \
|
||||
%{!mfp64: \
|
||||
%{mgp32:-D__mips_fpr=32} \
|
||||
%{!mgp32: %(cpp_fpr_spec)}}} \
|
||||
%{msingle-float: \
|
||||
%{!msoft-float:-D__mips_single_float}} \
|
||||
%{m4650: \
|
||||
%{!msoft-float:-D__mips_single_float}} \
|
||||
%{msoft-float:-D__mips_soft_float} \
|
||||
%{mabi=eabi:-D__mips_eabi} \
|
||||
%{mips16:%{!mno-mips16:-D__mips16}} \
|
||||
%{EB:-D__MIPSEB__} %{EL:-D__MIPSEL__} \
|
||||
%{!EB:%{!EL:%(subtarget_endian_default)}} \
|
||||
%(subtarget_cpp_spec) "
|
||||
|
||||
/* Extra specs we need. */
|
||||
#undef SUBTARGET_EXTRA_SPECS
|
||||
#define SUBTARGET_EXTRA_SPECS \
|
||||
|
|
|
@ -53,16 +53,17 @@ Boston, MA 02111-1307, USA. */
|
|||
support. */
|
||||
#undef SET_ASM_OP
|
||||
|
||||
/* Run-time target specifications. */
|
||||
#if TARGET_ENDIAN_DEFAULT != 0
|
||||
#define CPP_PREDEFINES "-D__SYSTYPE_BSD__ -D__NO_LEADING_UNDERSCORES__ \
|
||||
-D__GP_SUPPORT__ -D__MIPSEB__ -D__unix__ -D__OpenBSD__ -D__mips__ \
|
||||
-Asystem=unix -Asystem=OpenBSD -Acpu=mips -Amachine=mips -Aendian=big"
|
||||
#else
|
||||
#define CPP_PREDEFINES "-D__SYSTYPE_BSD__ -D__NO_LEADING_UNDERSCORES__ \
|
||||
-D__GP_SUPPORT__ -D__MIPSEL__ -D__unix__ -D__OpenBSD__ -D__mips__ \
|
||||
-Asystem=unix -Asystem=OpenBSD -Acpu=mips -Amachine=mips -Aendian=little"
|
||||
#endif
|
||||
#define TARGET_OS_CPP_BUILTINS() \
|
||||
do { \
|
||||
builtin_define ("__unix__"); \
|
||||
builtin_define ("__SYSTYPE_BSD__"); \
|
||||
builtin_define ("__NO_LEADING_UNDERSCORES__"); \
|
||||
builtin_define ("__GP_SUPPORT__"); \
|
||||
builtin_define ("__OpenBSD__"); \
|
||||
builtin_assert ("system=unix"); \
|
||||
builtin_assert ("system=OpenBSD"); \
|
||||
builtin_assert ("machine=mips"); \
|
||||
} while (0)
|
||||
|
||||
/* Layout of source language data types. */
|
||||
|
||||
|
|
|
@ -21,6 +21,8 @@ Boston, MA 02111-1307, USA. */
|
|||
|
||||
/* Specify predefined symbols in preprocessor. */
|
||||
|
||||
#undef CPP_PREDEFINES
|
||||
#define CPP_PREDEFINES "-Dmips -DMIPSEB -D_mips -D_MIPSEB \
|
||||
-D__rtems__ -Asystem=rtems"
|
||||
#define TARGET_OS_CPP_BUILTINS() \
|
||||
do { \
|
||||
builtin_define ("__rtems__"); \
|
||||
builtin_assert ("system=rtems"); \
|
||||
} while (0)
|
||||
|
|
|
@ -20,10 +20,11 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
|
|||
Boston, MA 02111-1307, USA. */
|
||||
|
||||
/* Specify predefined symbols in preprocessor. */
|
||||
|
||||
#undef CPP_PREDEFINES
|
||||
#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000 \
|
||||
-D__rtems__ -Asystem=rtems"
|
||||
#define TARGET_OS_CPP_BUILTINS() \
|
||||
do { \
|
||||
builtin_define ("__rtems__"); \
|
||||
builtin_assert ("system=rtems"); \
|
||||
} while (0)
|
||||
|
||||
#undef EXTRA_SECTIONS
|
||||
#define EXTRA_SECTIONS in_sdata
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/* Definitions of target machine for GNU compiler. SNI SINIX version.
|
||||
Copyright (C) 1996, 1997, 1999, 2000 Free Software Foundation, Inc.
|
||||
Copyright (C) 1996, 1997, 1999, 2000, 2002 Free Software Foundation, Inc.
|
||||
Contributed by Marco Walther (Marco.Walther@mch.sni.de).
|
||||
|
||||
This file is part of GNU CC.
|
||||
|
@ -21,10 +21,18 @@ Boston, MA 02111-1307, USA. */
|
|||
|
||||
#define MIPS_SVR4
|
||||
|
||||
#define CPP_PREDEFINES "\
|
||||
-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_SVR4 -Dsinix -DSNI \
|
||||
-D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_SVR4 \
|
||||
-Asystem=unix -Asystem=svr4 -Acpu=mips -Amachine=mips"
|
||||
#define TARGET_OS_CPP_BUILTINS() \
|
||||
do { \
|
||||
builtin_define_std ("host_mips"); \
|
||||
builtin_define_std ("SYSTYPE_SVR4"); \
|
||||
builtin_define_std ("unix"); \
|
||||
builtin_define_std ("mips"); \
|
||||
builtin_define_std ("sinix"); \
|
||||
builtin_define_std ("SNI"); \
|
||||
builtin_assert ("system=unix"); \
|
||||
builtin_assert ("system=svr4"); \
|
||||
builtin_assert ("machine=mips"); \
|
||||
} while (0)
|
||||
|
||||
#define LINK_SPEC "\
|
||||
%{G*} \
|
||||
|
|
|
@ -614,7 +614,8 @@ You can also test for the C dialect being compiled. The variable
|
|||
or @code{clk_objective_c}. Note that if we are preprocessing
|
||||
assembler, this variable will be @code{clk_c} but the function-like
|
||||
macro @code{preprocessing_asm_p()} will return true, so you might want
|
||||
to check for that first.
|
||||
to check for that first. If you need to check for strict ANSI, the
|
||||
variable @code{flag_iso} can be used.
|
||||
|
||||
With @code{TARGET_OS_CPP_BUILTINS} this macro obsoletes the
|
||||
@code{CPP_PREDEFINES} target macro.
|
||||
|
|
Loading…
Reference in New Issue