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rs6000.md (ltu<mode>): Convert to mode macro. 

* config/rs6000/rs6000.md (ltu<mode>): Convert to mode macro.
        (neg_ltu<mode>): Same.
        (gtu<mode>): Same.
        (neg_gtu<mode>): Same.

From-SVN: r103159
This commit is contained in:
David Edelsohn 2005-08-16 15:13:40 +00:00 committed by David Edelsohn
parent d110b74089
commit ce45ef468c
2 changed files with 36 additions and 70 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2005-08-16 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.md (ltu<mode>): Convert to mode macro.
(neg_ltu<mode>): Same.
(gtu<mode>): Same.
(neg_gtu<mode>): Same.
2005-08-16 Volker Reichelt <reichelt@igpm.rwth-aachen.de>
* builtins.c (expand_builtin_strcat): Remove superfluous call to fold.

99
gcc/config/rs6000/rs6000.md
View File

@ -11321,7 +11321,7 @@
;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
;; since it nabs/sr is just as fast.
(define_insn "*ne0"
(define_insn "*ne0si"
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
(lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
(const_int 31)))
@ -11331,7 +11331,7 @@
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
(define_insn "*ne0di"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
(const_int 63)))
@ -12024,26 +12024,15 @@
"doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
(define_insn_and_split ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
"TARGET_32BIT"
(define_insn_and_split "*ltu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
(ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
(match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
""
"#"
"TARGET_32BIT"
[(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (neg:SI (match_dup 0)))]
"")
(define_insn_and_split ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
"TARGET_64BIT"
"#"
"TARGET_64BIT"
[(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (neg:DI (match_dup 0)))]
""
[(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
(set (match_dup 0) (neg:P (match_dup 0)))]
"")
(define_insn ""
@ -12172,22 +12161,11 @@
(const_int 0)))]
"")
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
"TARGET_32BIT"
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
(neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
(match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
"TARGET_64BIT"
(define_insn "*neg_ltu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
(neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
(match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
""
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
@ -12953,26 +12931,15 @@
"doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
(define_insn_and_split ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
(define_insn_and_split "*gtu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "reg_or_short_operand" "rI")))]
""
"#"
"TARGET_32BIT"
[(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (neg:SI (match_dup 0)))]
"")
(define_insn_and_split ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
"#"
"TARGET_64BIT"
[(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
(set (match_dup 0) (neg:DI (match_dup 0)))]
""
[(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
(set (match_dup 0) (neg:P (match_dup 0)))]
"")
(define_insn ""
@ -13199,23 +13166,15 @@
(const_int 0)))]
"")
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"TARGET_32BIT"
(define_insn "*neg_gtu<mode>"
[(set (match_operand:P 0 "gpc_reg_operand" "=r")
(neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
(match_operand:P 2 "reg_or_short_operand" "rI"))))]
""
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
[(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "reg_or_short_operand" "rI"))))]
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;subfe %0,%0,%0"
[(set_attr "type" "two")
(set_attr "length" "8")])
;; Define both directions of branch and return. If we need a reload
;; register, we'd rather use CR0 since it is much easier to copy a
@ -13464,7 +13423,7 @@
operands[4] = gen_reg_rtx (DImode);
}")
(define_insn ""
(define_insn "*tablejump<mode>_internal1"
[(set (pc)
(match_operand:P 0 "register_operand" "c,*l"))
(use (label_ref (match_operand 1 "" "")))]