rs6000.md: Enable patterns using rlwinm for PowerPC64.
* config/rs6000/rs6000.md: Enable patterns using rlwinm for PowerPC64. Replace "T" and "S" constraints with "n" when the predicate will do. Formatting fixes. (extzvsi_internal2): Use "andi.", "andis." and attr type of "compare" as for extzvsi_internal1. From-SVN: r55770
This commit is contained in:
Alan Modra
Alan Modra
parent
7702af3606
commit
ce71f7547b
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@ -1,3 +1,11 @@
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2002-07-26 Alan Modra <amodra@bigpond.net.au>
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* config/rs6000/rs6000.md: Enable patterns using rlwinm for
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PowerPC64. Replace "T" and "S" constraints with "n" when the
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predicate will do. Formatting fixes.
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(extzvsi_internal2): Use "andi.", "andis." and attr type of "compare"
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as for extzvsi_internal1.
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2002-07-25 Neil Booth <neil@daikokuya.co.uk>
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* dwarfout.c (VERSION_ASM_OP, DERIV_BEGIN_LABEL_FMT,
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@ -3811,7 +3811,7 @@
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(match_operand:SI 3 "const_int_operand" "i,i"))
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(const_int 0)))
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(clobber (match_scratch:SI 4 "=r,r"))]
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"! TARGET_POWERPC64"
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""
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"*
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{
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int start = INTVAL (operands[3]) & 31;
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@ -3853,7 +3853,7 @@
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(match_operand:SI 3 "const_int_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 4 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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"reload_completed"
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[(set (match_dup 4)
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(zero_extract:SI (match_dup 1) (match_dup 2)
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(match_dup 3)))
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@ -3870,7 +3870,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
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"! TARGET_POWERPC64"
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""
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"*
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{
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int start = INTVAL (operands[3]) & 31;
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@ -3880,10 +3880,14 @@
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if (which_alternative == 1)
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return \"#\";
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if (start >= 16 && start + size == 32)
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if ((start > 0 && start + size <= 16) || start >= 16)
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{
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operands[3] = GEN_INT ((1 << (32 - start)) - 1);
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return \"{andil.|andi.} %0,%1,%3\";
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operands[3] = GEN_INT (((1 << (16 - (start & 15)))
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- (1 << (16 - (start & 15) - size))));
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if (start < 16)
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return \"{andiu.|andis.} %0,%1,%3\";
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else
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return \"{andil.|andi.} %0,%1,%3\";
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}
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if (start + size >= 32)
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@ -3892,7 +3896,7 @@
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operands[3] = GEN_INT (start + size);
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return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
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}"
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[(set_attr "type" "delayed_compare")
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[(set_attr "type" "compare")
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(set_attr "length" "4,8")])
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(define_split
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@ -3903,7 +3907,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
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"! TARGET_POWERPC64 && reload_completed"
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"reload_completed"
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[(set (match_dup 0)
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(zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
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(set (match_dup 4)
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@ -3986,7 +3990,7 @@
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(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r"))]
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"! TARGET_POWERPC64"
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""
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"@
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{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
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#"
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@ -3999,7 +4003,7 @@
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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"reload_completed"
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[(set (match_dup 3)
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(rotate:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 0)
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@ -4014,7 +4018,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(rotate:SI (match_dup 1) (match_dup 2)))]
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"! TARGET_POWERPC64"
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""
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"@
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{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
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#"
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@ -4028,7 +4032,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(rotate:SI (match_dup 1) (match_dup 2)))]
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"! TARGET_POWERPC64 && reload_completed"
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"reload_completed"
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[(set (match_dup 0)
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(rotate:SI (match_dup 1) (match_dup 2)))
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(set (match_dup 3)
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@ -4040,7 +4044,7 @@
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "reg_or_cint_operand" "ri"))
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(match_operand:SI 3 "mask_operand" "T")))]
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(match_operand:SI 3 "mask_operand" "n")))]
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""
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"{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
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@ -4049,10 +4053,10 @@
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(compare:CC (and:SI
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(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
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(match_operand:SI 3 "mask_operand" "T,T"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(clobber (match_scratch:SI 4 "=r,r"))]
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"! TARGET_POWERPC64"
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""
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"@
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{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
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#"
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@ -4067,7 +4071,7 @@
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(match_operand:SI 3 "mask_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 4 ""))]
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"! TARGET_POWERPC64 && reload_completed"
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"reload_completed"
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[(set (match_dup 4)
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(and:SI (rotate:SI (match_dup 1)
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(match_dup 2))
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@ -4082,11 +4086,11 @@
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(compare:CC (and:SI
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(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
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(match_operand:SI 3 "mask_operand" "T,T"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"! TARGET_POWERPC64"
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""
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"@
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{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
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#"
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@ -4102,7 +4106,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"! TARGET_POWERPC64 && reload_completed"
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"reload_completed"
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[(set (match_dup 0)
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(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(set (match_dup 4)
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@ -4420,7 +4424,7 @@
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i"))
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(match_operand:SI 3 "mask_operand" "T")))]
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(match_operand:SI 3 "mask_operand" "n")))]
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"includes_lshift_p (operands[2], operands[3])"
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"{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
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@ -4429,10 +4433,10 @@
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(compare:CC
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(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "const_int_operand" "i,i"))
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(match_operand:SI 3 "mask_operand" "T,T"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(clobber (match_scratch:SI 4 "=r,r"))]
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"! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
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"includes_lshift_p (operands[2], operands[3])"
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"@
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{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
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#"
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@ -4447,7 +4451,7 @@
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(match_operand:SI 3 "mask_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 4 ""))]
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"! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
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"includes_lshift_p (operands[2], operands[3]) && reload_completed"
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[(set (match_dup 4)
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(and:SI (ashift:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))
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@ -4461,11 +4465,11 @@
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(compare:CC
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(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "const_int_operand" "i,i"))
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(match_operand:SI 3 "mask_operand" "T,T"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
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"includes_lshift_p (operands[2], operands[3])"
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"@
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{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
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#"
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@ -4481,7 +4485,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
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"includes_lshift_p (operands[2], operands[3]) && reload_completed"
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[(set (match_dup 0)
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(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(set (match_dup 4)
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@ -4659,7 +4663,7 @@
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i"))
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(match_operand:SI 3 "mask_operand" "T")))]
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(match_operand:SI 3 "mask_operand" "n")))]
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"includes_rshift_p (operands[2], operands[3])"
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"{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
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@ -4668,10 +4672,10 @@
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(compare:CC
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(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "const_int_operand" "i,i"))
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(match_operand:SI 3 "mask_operand" "T,T"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(clobber (match_scratch:SI 4 "=r,r"))]
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"! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
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"includes_rshift_p (operands[2], operands[3])"
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"@
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{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
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#"
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@ -4686,7 +4690,7 @@
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(match_operand:SI 3 "mask_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 4 ""))]
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"! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
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"includes_rshift_p (operands[2], operands[3]) && reload_completed"
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[(set (match_dup 4)
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(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))
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@ -4700,11 +4704,11 @@
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(compare:CC
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(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "const_int_operand" "i,i"))
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(match_operand:SI 3 "mask_operand" "T,T"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
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"includes_rshift_p (operands[2], operands[3])"
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"@
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{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
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#"
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@ -4720,7 +4724,7 @@
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
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"includes_rshift_p (operands[2], operands[3]) && reload_completed"
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[(set (match_dup 0)
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(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(set (match_dup 4)
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@ -6834,7 +6838,7 @@
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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(and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
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(match_operand:DI 2 "reg_or_cint_operand" "ri"))
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(match_operand:DI 3 "mask64_operand" "S")))]
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(match_operand:DI 3 "mask64_operand" "n")))]
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"TARGET_POWERPC64"
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"rld%I2c%B3 %0,%1,%H2,%S3")
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@ -6843,7 +6847,7 @@
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(compare:CC (and:DI
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(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
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(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
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(match_operand:DI 3 "mask64_operand" "S,S"))
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(match_operand:DI 3 "mask64_operand" "n,n"))
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(const_int 0)))
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(clobber (match_scratch:DI 4 "=r,r"))]
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"TARGET_POWERPC64"
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@ -6876,7 +6880,7 @@
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(compare:CC (and:DI
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(rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
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(match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
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(match_operand:DI 3 "mask64_operand" "S,S"))
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(match_operand:DI 3 "mask64_operand" "n,n"))
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(const_int 0)))
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(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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(and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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@ -7291,7 +7295,7 @@
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
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(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i"))
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(match_operand:DI 3 "mask64_operand" "S")))]
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(match_operand:DI 3 "mask64_operand" "n")))]
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"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
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"rldicr %0,%1,%H2,%S3")
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@ -7300,7 +7304,7 @@
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(compare:CC
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(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "const_int_operand" "i,i"))
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(match_operand:DI 3 "mask64_operand" "S,S"))
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(match_operand:DI 3 "mask64_operand" "n,n"))
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(const_int 0)))
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(clobber (match_scratch:DI 4 "=r,r"))]
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"TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
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@ -7333,7 +7337,7 @@
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(compare:CC
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(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "const_int_operand" "i,i"))
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(match_operand:DI 3 "mask64_operand" "S,S"))
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(match_operand:DI 3 "mask64_operand" "n,n"))
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(const_int 0)))
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(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
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(and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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@ -11219,7 +11223,7 @@
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(set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
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(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
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(match_dup 3)))]
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"! TARGET_POWERPC64"
|
||||
""
|
||||
"*
|
||||
{
|
||||
int is_bit = ccr_bit (operands[1], 1);
|
||||
|
|
@ -11254,7 +11258,7 @@
|
|||
(set (match_operand:SI 4 "gpc_reg_operand" "")
|
||||
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
|
||||
(match_dup 3)))]
|
||||
"! TARGET_POWERPC64 && reload_completed"
|
||||
"reload_completed"
|
||||
[(set (match_dup 4)
|
||||
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
|
||||
(match_dup 3)))
|
||||
|
|
@ -11620,9 +11624,9 @@
|
|||
(clobber (match_scratch:SI 4 ""))]
|
||||
"! TARGET_POWERPC64 && reload_completed"
|
||||
[(parallel [(set (match_dup 3)
|
||||
(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
|
||||
(const_int 31))
|
||||
(match_dup 2)))
|
||||
(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
|
||||
(const_int 31))
|
||||
(match_dup 2)))
|
||||
(clobber (match_dup 4))])
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 3)
|
||||
|
|
@ -15105,7 +15109,6 @@
|
|||
(define_insn "altivec_vmrglb"
|
||||
[(set (match_operand:V16QI 0 "register_operand" "=v")
|
||||
(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
|
||||
|
||||
(parallel [(const_int 0)
|
||||
(const_int 1)
|
||||
(const_int 2)
|
||||
|
|
|
|||
Loading…
Reference in New Issue