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cfglayout.c, [...]: Fix comment typos. 

* cfglayout.c, config/arm/arm.c, config/arm/cortex-a8.md,
	config/arm/neon-schedgen.ml, config/arm/neon.ml,
	config/arm/vec-common.md, config/ia64/div.md, cselib.c,
	df-core.c, df.h, dominance.c, optabs.c, opts.c, reg-stack.c,
	regstat.c, target.h, tree-ssa-live.c, tree-ssa-pre.c,
	tree-vect-transform.c, tree.def: Fix comment typos.  Follow
	spelling conventions.
	* doc/invoke.texi: Follow spelling conventions.

From-SVN: r127030
This commit is contained in:
Kazu Hirata 2007-07-28 23:55:00 +00:00 committed by Kazu Hirata
parent 1207ac677d
commit cea618ac1f
22 changed files with 39 additions and 28 deletions
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11
gcc/ChangeLog
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@ -1,3 +1,14 @@
2007-07-28 Kazu Hirata <kazu@codesourcery.com>
* cfglayout.c, config/arm/arm.c, config/arm/cortex-a8.md,
config/arm/neon-schedgen.ml, config/arm/neon.ml,
config/arm/vec-common.md, config/ia64/div.md, cselib.c,
df-core.c, df.h, dominance.c, optabs.c, opts.c, reg-stack.c,
regstat.c, target.h, tree-ssa-live.c, tree-ssa-pre.c,
tree-vect-transform.c, tree.def: Fix comment typos. Follow
spelling conventions.
* doc/invoke.texi: Follow spelling conventions.
2007-07-29 Vladimir Yanovsky <yanov@il.ibm.com>
Revital Eres <eres@il.ibm.com>

2
gcc/cfglayout.c
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@ -1001,7 +1001,7 @@ force_one_exit_fallthru (void)
redirect_edge_and_branch_force (e, forwarder);
}
/* Fix up the chain of blocks -- make FORWARDER immediately preceed the
/* Fix up the chain of blocks -- make FORWARDER immediately precede the
exit block. */
FOR_EACH_BB (bb)
{

6
gcc/config/arm/arm.c
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@ -6083,7 +6083,7 @@ neon_valid_immediate (rtx op, enum machine_mode mode, int inverse,
{
unsigned HOST_WIDE_INT imm = 0;
/* Un-invert bytes of recognized vector, if neccessary. */
/* Un-invert bytes of recognized vector, if necessary. */
if (invmask != 0)
for (i = 0; i < idx; i++)
bytes[i] ^= invmask;
@ -6212,7 +6212,7 @@ neon_pairwise_reduce (rtx op0, rtx op1, enum machine_mode mode,
}
}
/* Initialise a vector with non-constant elements. FIXME: We can do better
/* Initialize a vector with non-constant elements. FIXME: We can do better
than the current implementation (building a vector on the stack and then
loading it) in many cases. See rs6000.c. */
@ -12664,7 +12664,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
break;
/* %# is a "break" sequence. It doesn't output anything, but is used to
seperate e.g. operand numbers from following text, if that text consists
separate e.g. operand numbers from following text, if that text consists
of further digits which we don't want to be part of the operand
number. */
case '#':

4
gcc/config/arm/cortex-a8.md
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@ -129,7 +129,7 @@
"arm_no_early_alu_shift_value_dep")
;; Multiplication instructions. These are categorized according to their
;; reservation behaviour and the need below to distinguish certain
;; reservation behavior and the need below to distinguish certain
;; varieties for bypasses. Results are available at the E5 stage
;; (but some of these are multi-cycle instructions which explains the
;; latencies below).
@ -245,7 +245,7 @@
;; reads the value to be stored at the start of E3 and the ALU insn
;; writes it at the end of E2. Move instructions actually produce the
;; result at the end of E1, but since we don't have delay slots, the
;; scheduling behaviour will be the same.
;; scheduling behavior will be the same.
(define_bypass 0 "cortex_a8_alu,cortex_a8_alu_shift,\
cortex_a8_alu_shift_reg,cortex_a8_mov"
"cortex_a8_store1_2,cortex_a8_store3_4"

4
gcc/config/arm/neon-schedgen.ml
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@ -63,7 +63,7 @@ type availability = Source of int
type guard = Guard_none | Guard_only_m | Guard_only_n | Guard_only_d
(* Reservation behaviours. All but the last row here correspond to one
(* Reservation behaviors. All but the last row here correspond to one
pipeline each. Each constructor will correspond to one
define_reservation. *)
type reservation =
@ -78,7 +78,7 @@ type reservation =
| Fmul_then_fadd | Fmul_then_fadd_2
(* This table must be kept as short as possible by conflating
entries with the same availability behaviour.
entries with the same availability behavior.
First components: instruction group names
Second components: availability requirements, in the order in which

4
gcc/config/arm/neon.ml
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@ -177,7 +177,7 @@ type opcode =
(* Set/extract lanes from a vector. *)
| Vget_lane
| Vset_lane
(* Initialise vector from bit pattern. *)
(* Initialize vector from bit pattern. *)
| Vcreate
(* Set all lanes to same value. *)
| Vdup_n
@ -227,7 +227,7 @@ type features =
names. *)
| Instruction_name of string list
(* Mark that the intrinsic yields no instructions, or expands to yield
behaviour that the test generator cannot test. *)
behavior that the test generator cannot test. *)
| No_op
(* Mark that the intrinsic has constant arguments that cannot be set
to the defaults (zero for pointers and one otherwise) in the test

2
gcc/config/arm/vec-common.md
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@ -42,7 +42,7 @@
})
;; Vector arithmetic. Expanders are blank, then unnamed insns implement
;; patterns seperately for IWMMXT and Neon.
;; patterns separately for IWMMXT and Neon.
(define_expand "add<mode>3"
[(set (match_operand:VALL 0 "s_register_operand" "")

2
gcc/config/ia64/div.md
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@ -195,7 +195,7 @@
operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
})
;; Reciprical approximation
;; Reciprocal approximation
(define_insn "recip_approx_rf"
[(set (match_operand:RF 0 "fr_register_operand" "=f")

2
gcc/cselib.c
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@ -953,7 +953,7 @@ cselib_expand_value_rtx (rtx orig, bitmap regs_active, int max_depth)
STACK_POINTER_REGNUM, FRAME_POINTER or the
HARD_FRAME_POINTER.
Thses expansions confuses the code that notices that
These expansions confuses the code that notices that
stores into the frame go dead at the end of the
function and that the frame is not effected by calls
to subroutines. If you allow the

2
gcc/df-core.c
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@ -144,7 +144,7 @@ There are four ways of doing the incremental scanning:
For most modern rtl passes, this is certainly the easiest way to
manage rescanning the insns. This technique also has the advantage
that the scanning information is always correct and can be relied
apon even after changes have been made to the instructions. This
upon even after changes have been made to the instructions. This
technique is contra indicated in several cases:
a) If def-use chains OR use-def chains (but not both) are built,

4
gcc/df.h
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@ -311,7 +311,7 @@ struct dataflow
struct df_mw_hardreg
{
rtx mw_reg; /* The multiword hardreg. */
/* These two bitfields are intentially oversized, in the hope that
/* These two bitfields are intentionally oversized, in the hope that
accesses to 16-bit fields will usually be quicker. */
ENUM_BITFIELD(df_ref_type) type : 16;
/* Used to see if the ref is read or write. */
@ -360,7 +360,7 @@ struct df_ref
unsigned int ref_order;
unsigned int regno; /* The register number referenced. */
/* These two bitfields are intentially oversized, in the hope that
/* These two bitfields are intentionally oversized, in the hope that
accesses to 16-bit fields will usually be quicker. */
ENUM_BITFIELD(df_ref_type) type : 16;
/* Type of ref. */

2
gcc/doc/invoke.texi
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@ -1858,7 +1858,7 @@ been permitted when this option was not used.
In new code it is better to use @option{-fvisibility=hidden} and
export those classes which are intended to be externally visible.
Unfortunately it is possible for code to rely, perhaps accidentally,
on the Visual Studio behaviour.
on the Visual Studio behavior.
Among the consequences of these changes are that static data members
of the same type with the same name but defined in different shared

2
gcc/dominance.c
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@ -1448,7 +1448,7 @@ debug_dominance_info (enum cdi_direction dir)
}
/* Prints to stderr representation of the dominance tree (for direction DIR)
rooted in ROOT, indented by INDENT tabelators. If INDENT_FIRST is false,
rooted in ROOT, indented by INDENT tabulators. If INDENT_FIRST is false,
the first line of the output is not indented. */
static void

2
gcc/optabs.c
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@ -4071,7 +4071,7 @@ emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size,
{
/* If we're not emitting a branch, callers are required to pass
operands in an order conforming to canonical RTL. We relax this
for commutative comparsions so callers using EQ don't need to do
for commutative comparisons so callers using EQ don't need to do
swapping by hand. */
gcc_assert (label || (comparison == swap_condition (comparison)));

2
gcc/opts.c
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@ -91,7 +91,7 @@ enum debug_info_level debug_info_level = DINFO_LEVEL_NONE;
generated in the object file of the corresponding source file.
Both of these case are handled when the base name of the file of
the struct definition matches the base name of the source file
of thet current compilation unit. This matching emits minimal
of the current compilation unit. This matching emits minimal
struct debugging information.
The base file name matching rule above will fail to emit debug

4
gcc/reg-stack.c
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@ -1355,9 +1355,9 @@ subst_stack_regs_pat (rtx insn, stack regstack, rtx pat)
}
/* Uninitialized USE might happen for functions returning uninitialized
value. We will properly initialize the USE on the edge to EXIT_BLOCK,
so it is safe to ignore the use here. This is consistent with behaviour
so it is safe to ignore the use here. This is consistent with behavior
of dataflow analyzer that ignores USE too. (This also imply that
forcingly initializing the register to NaN here would lead to ICE later,
forcibly initializing the register to NaN here would lead to ICE later,
since the REG_DEAD notes are not issued.) */
break;

2
gcc/regstat.c
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@ -395,7 +395,7 @@ regstat_get_setjmp_crosses (void)
Process REG_N_CALLS_CROSSED.
This is used by sched_deps. A good implementation of sched-deps
would really process the blocks directly rather than going thur
would really process the blocks directly rather than going through
lists of insns. If it did this, it could use the exact regs that
cross an individual call rather than using this info that merges
the info for all calls.

2
gcc/target.h
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@ -420,7 +420,7 @@ struct gcc_target
int (*builtin_vectorization_cost) (bool);
/* Return true if vector alignment is reachable (by peeling N
interations) for the given type. */
iterations) for the given type. */
bool (* vector_alignment_reachable) (tree, bool);
} vectorize;

2
gcc/tree-ssa-live.c
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@ -461,7 +461,7 @@ mark_scope_block_unused (tree scope)
or there is precisely one subblocks and the block
has same abstract origin as outer block and declares
no variables, so it is pure wrapper.
When we are not outputting full debug info, we also elliminate dead variables
When we are not outputting full debug info, we also eliminate dead variables
out of scope blocks to let them to be recycled by GGC and to save copying work
done by the inliner. */

2
gcc/tree-ssa-pre.c
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@ -1431,7 +1431,7 @@ bitmap_find_leader (bitmap_set_t set, tree val)
return NULL;
}
/* Determine if EXPR, a memory expressionn, is ANTIC_IN at the top of
/* Determine if EXPR, a memory expression, is ANTIC_IN at the top of
BLOCK by seeing if it is not killed in the block. Note that we are
only determining whether there is a store that kills it. Because
of the order in which clean iterates over values, we are guaranteed

2
gcc/tree-vect-transform.c
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@ -265,7 +265,7 @@ vect_estimate_min_profitable_iters (loop_vec_info loop_vinfo)
/* If the number of iterations is unknown, or the
peeling-for-misalignment amount is unknown, we eill have to generate
a runtime test to test the loop count agains the threshold. */
a runtime test to test the loop count against the threshold. */
if (!LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo)
|| (byte_misalign < 0))
runtime_test = true;

2
gcc/tree.def
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@ -884,7 +884,7 @@ DEFTREECODE (EH_FILTER_EXPR, "eh_filter_expr", tcc_statement, 2)
has no value and generates no executable code. It is only used for
type based alias analysis. This is generated by C++ placement new.
CHANGE_DYNAMIC_TYPE_NEW_TYPE, the first operand, is the new type.
CHNAGE_DYNAMIC_TYPE_LOCATION, the second operand, is the location
CHANGE_DYNAMIC_TYPE_LOCATION, the second operand, is the location
whose type is being changed. */
DEFTREECODE (CHANGE_DYNAMIC_TYPE_EXPR, "change_dynamic_type_expr",
tcc_statement, 2)