re PR target/53228 (target attributes in libcpp/lex.c cause illegal instructions to be used elsewhere)

PR target/53228
	* config/i386/i386.h (X86_ARCH_CMOV): Rename from X86_ARCH_CMOVE.
	(TARGET_CMOV): Rename from TARGET_CMOVE.
	(TARGET_CMOVE): New define.
	* config/i386/i386.c (ix86_option_override_internal): Use TARGET_CMOV.
	Do not set TARGET_CMOVE here.

From-SVN: r187168
This commit is contained in:
Uros Bizjak 2012-05-04 18:42:23 +02:00
parent 33d11b9745
commit cef31f9c56
3 changed files with 22 additions and 18 deletions

View File

@ -1,3 +1,12 @@
2012-05-04 Uros Bizjak <ubizjak@gmail.com>
PR target/53228
* config/i386/i386.h (X86_ARCH_CMOV): Rename from X86_ARCH_CMOVE.
(TARGET_CMOV): Rename from TARGET_CMOVE.
(TARGET_CMOVE): New define.
* config/i386/i386.c (ix86_option_override_internal): Use TARGET_CMOV.
Do not set TARGET_CMOVE here.
2012-05-04 Dodji Seketeli <dodji@redhat.com>
Enable -Wunused-local-typedefs when -Wall or -Wunused is on
@ -222,8 +231,7 @@
pointer.
(__assert_gimple_bb_smaller_rtl_bb): Asserting typedef.
* cfgexpand.c (expand_gimple_basic_block): Clear all il.gimple
members.
* cfgexpand.c (expand_gimple_basic_block): Clear all il.gimple members.
* gimple-iterator.c (gimple_stmt_iterator): Don't special case
NULL il.gimple, which can't happen anymore.
* gimple.h (bb_seq): il.gimple can't be NULL.
@ -248,8 +256,7 @@
* tree-ssa-pre.c (valid_in_sets): Remove checking of trapping
operations.
(prune_clobbered_mems): Do it here. Do not uselessly sort
expressions.
(prune_clobbered_mems): Do it here. Do not uselessly sort expressions.
(compute_avail): Do not add possibly trapping operations to
EXP_GEN if they might not be executed in the block.
@ -609,8 +616,7 @@
* config/i386/driver-i386.c (host_detect_local_cpu): Detect
HLE support.
* config/i386/i386-protos.h (ix86_generate_hle_prefix): New.
* config/i386/i386-c.c (ix86_target_macros_internal): Set
HLE defines.
* config/i386/i386-c.c (ix86_target_macros_internal): Set HLE defines.
(ix86_target_string)<-mhle>: New.
(ix86_valid_target_attribute_inner_p) <OPT_mhle>: Ditto.
* config/i386/i386.c (ix86_target_string) <OPTION_MASK_ISA_HLE>: New.
@ -657,8 +663,7 @@
* fold-const.c (div_if_zero_remainder): sizetypes no longer
sign-extend.
(int_const_binop_1): New worker for int_const_binop with
overflowable parameter. Pass it through
to force_fit_type_double.
overflowable parameter. Pass it through to force_fit_type_double.
(int_const_binop): Wrap around int_const_binop_1 with overflowable
equal to one.
(size_binop_loc): Call int_const_binop_1 with overflowable equal

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@ -2190,7 +2190,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST];
/* Feature tests against the various architecture variations, used to create
ix86_arch_features based on the processor mask. */
static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
/* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
/* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
~(m_386 | m_486 | m_PENT | m_K6),
/* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
@ -3504,7 +3504,7 @@ ix86_option_override_internal (bool main_args_p)
-mtune (rather than -march) points us to a processor that has them.
However, the VIA C3 gives a SIGILL, so we only do that for i686 and
higher processors. */
if (TARGET_CMOVE
if (TARGET_CMOV
&& (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
x86_prefetch_sse = true;
break;
@ -3780,12 +3780,6 @@ ix86_option_override_internal (bool main_args_p)
target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
}
/* For sane SSE instruction set generation we need fcomi instruction.
It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
expands to a sequence that includes conditional move. */
if (TARGET_SSE || TARGET_RDRND)
TARGET_CMOVE = 1;
/* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
{
char *p;

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@ -430,7 +430,7 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
/* Feature tests against the various architecture variations. */
enum ix86_arch_indices {
X86_ARCH_CMOVE, /* || TARGET_SSE */
X86_ARCH_CMOV,
X86_ARCH_CMPXCHG,
X86_ARCH_CMPXCHG8B,
X86_ARCH_XADD,
@ -441,12 +441,17 @@ enum ix86_arch_indices {
extern unsigned char ix86_arch_features[X86_ARCH_LAST];
#define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
/* For sane SSE instruction set generation we need fcomi instruction.
It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
expands to a sequence that includes conditional move. */
#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
extern int x86_prefetch_sse;