re PR target/53228 (target attributes in libcpp/lex.c cause illegal instructions to be used elsewhere)
PR target/53228 * config/i386/i386.h (X86_ARCH_CMOV): Rename from X86_ARCH_CMOVE. (TARGET_CMOV): Rename from TARGET_CMOVE. (TARGET_CMOVE): New define. * config/i386/i386.c (ix86_option_override_internal): Use TARGET_CMOV. Do not set TARGET_CMOVE here. From-SVN: r187168
This commit is contained in:
Uros Bizjak
parent
33d11b9745
commit
cef31f9c56
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@ -1,3 +1,12 @@
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2012-05-04 Uros Bizjak <ubizjak@gmail.com>
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PR target/53228
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* config/i386/i386.h (X86_ARCH_CMOV): Rename from X86_ARCH_CMOVE.
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(TARGET_CMOV): Rename from TARGET_CMOVE.
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(TARGET_CMOVE): New define.
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* config/i386/i386.c (ix86_option_override_internal): Use TARGET_CMOV.
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Do not set TARGET_CMOVE here.
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2012-05-04 Dodji Seketeli <dodji@redhat.com>
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Enable -Wunused-local-typedefs when -Wall or -Wunused is on
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@ -222,8 +231,7 @@
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pointer.
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(__assert_gimple_bb_smaller_rtl_bb): Asserting typedef.
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* cfgexpand.c (expand_gimple_basic_block): Clear all il.gimple
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members.
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* cfgexpand.c (expand_gimple_basic_block): Clear all il.gimple members.
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* gimple-iterator.c (gimple_stmt_iterator): Don't special case
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NULL il.gimple, which can't happen anymore.
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* gimple.h (bb_seq): il.gimple can't be NULL.
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@ -248,8 +256,7 @@
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* tree-ssa-pre.c (valid_in_sets): Remove checking of trapping
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operations.
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(prune_clobbered_mems): Do it here. Do not uselessly sort
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expressions.
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(prune_clobbered_mems): Do it here. Do not uselessly sort expressions.
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(compute_avail): Do not add possibly trapping operations to
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EXP_GEN if they might not be executed in the block.
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@ -609,8 +616,7 @@
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* config/i386/driver-i386.c (host_detect_local_cpu): Detect
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HLE support.
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* config/i386/i386-protos.h (ix86_generate_hle_prefix): New.
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* config/i386/i386-c.c (ix86_target_macros_internal): Set
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HLE defines.
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* config/i386/i386-c.c (ix86_target_macros_internal): Set HLE defines.
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(ix86_target_string)<-mhle>: New.
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(ix86_valid_target_attribute_inner_p) <OPT_mhle>: Ditto.
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* config/i386/i386.c (ix86_target_string) <OPTION_MASK_ISA_HLE>: New.
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@ -657,8 +663,7 @@
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* fold-const.c (div_if_zero_remainder): sizetypes no longer
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sign-extend.
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(int_const_binop_1): New worker for int_const_binop with
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overflowable parameter. Pass it through
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to force_fit_type_double.
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overflowable parameter. Pass it through to force_fit_type_double.
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(int_const_binop): Wrap around int_const_binop_1 with overflowable
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equal to one.
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(size_binop_loc): Call int_const_binop_1 with overflowable equal
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@ -2190,7 +2190,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST];
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/* Feature tests against the various architecture variations, used to create
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ix86_arch_features based on the processor mask. */
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static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
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/* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
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/* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
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~(m_386 | m_486 | m_PENT | m_K6),
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/* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
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@ -3504,7 +3504,7 @@ ix86_option_override_internal (bool main_args_p)
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-mtune (rather than -march) points us to a processor that has them.
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However, the VIA C3 gives a SIGILL, so we only do that for i686 and
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higher processors. */
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if (TARGET_CMOVE
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if (TARGET_CMOV
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&& (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
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x86_prefetch_sse = true;
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break;
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@ -3780,12 +3780,6 @@ ix86_option_override_internal (bool main_args_p)
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target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
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}
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/* For sane SSE instruction set generation we need fcomi instruction.
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It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
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expands to a sequence that includes conditional move. */
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if (TARGET_SSE || TARGET_RDRND)
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TARGET_CMOVE = 1;
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/* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
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{
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char *p;
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@ -430,7 +430,7 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
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/* Feature tests against the various architecture variations. */
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enum ix86_arch_indices {
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X86_ARCH_CMOVE, /* || TARGET_SSE */
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X86_ARCH_CMOV,
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X86_ARCH_CMPXCHG,
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X86_ARCH_CMPXCHG8B,
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X86_ARCH_XADD,
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@ -441,12 +441,17 @@ enum ix86_arch_indices {
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extern unsigned char ix86_arch_features[X86_ARCH_LAST];
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#define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
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#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV]
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#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
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#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
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#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
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#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
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/* For sane SSE instruction set generation we need fcomi instruction.
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It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic
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expands to a sequence that includes conditional move. */
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#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND)
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#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
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extern int x86_prefetch_sse;
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