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i386.md: New peephole2's to convert imul by 3, 5 or 9 into the equivalent lea instruction. 

* config/i386/i386.md: New peephole2's to convert imul by 3, 5 or
	9 into the equivalent lea instruction.

Co-Authored-By: Richard Henderson <rth@redhat.com>

From-SVN: r85366
This commit is contained in:
Roger Sayle 2004-07-31 00:03:38 +00:00 committed by Roger Sayle
parent 0534fa5652
commit cf14e33d62
2 changed files with 69 additions and 0 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2004-07-30 Roger Sayle <roger@eyesopen.com>
Richard Henderson <rth@redhat.com>
* config/i386/i386.md: New peephole2's to convert imul by 3, 5 or
9 into the equivalent lea instruction.
2004-07-30 Richard Henderson <rth@redhat.com>
* gimplify.c (gimplify_expr) <case CONST_DECL>: Don't replace

63
gcc/config/i386/i386.md
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@ -19326,6 +19326,69 @@
(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
"")
;; Convert imul by three, five and nine into lea
(define_peephole2
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
"INTVAL (operands[2]) == 3
|| INTVAL (operands[2]) == 5
|| INTVAL (operands[2]) == 9"
[(set (match_dup 0)
(plus:SI (mult:SI (match_dup 1) (match_dup 2))
(match_dup 1)))]
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
(define_peephole2
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
"!optimize_size
&& (INTVAL (operands[2]) == 3
|| INTVAL (operands[2]) == 5
|| INTVAL (operands[2]) == 9)"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 0)
(plus:SI (mult:SI (match_dup 0) (match_dup 2))
(match_dup 0)))]
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
(define_peephole2
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(mult:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT
&& (INTVAL (operands[2]) == 3
|| INTVAL (operands[2]) == 5
|| INTVAL (operands[2]) == 9)"
[(set (match_dup 0)
(plus:DI (mult:DI (match_dup 1) (match_dup 2))
(match_dup 1)))]
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
(define_peephole2
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
(match_operand:DI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT
&& !optimize_size
&& (INTVAL (operands[2]) == 3
|| INTVAL (operands[2]) == 5
|| INTVAL (operands[2]) == 9)"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 0)
(plus:DI (mult:DI (match_dup 0) (match_dup 2))
(match_dup 0)))]
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
;; Imul $32bit_imm, mem, reg is vector decoded, while
;; imul $32bit_imm, reg, reg is direct decoded.
(define_peephole2