From cf4d516a507431bf8a42bf9aa2502b8a1ee34bc7 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Wed, 18 May 2016 11:24:15 +0200 Subject: [PATCH] sse.md (_palignr): Use constraint x instead of v in second alternative, add avx512bw alternative. * config/i386/sse.md (_palignr): Use constraint x instead of v in second alternative, add avx512bw alternative. * gcc.target/i386/avx512vl-vpalignr-3.c: New test. * gcc.target/i386/avx512bw-vpalignr-3.c: New test. From-SVN: r236368 --- gcc/ChangeLog | 4 +++ gcc/config/i386/sse.md | 15 +++++----- gcc/testsuite/ChangeLog | 3 ++ .../gcc.target/i386/avx512bw-vpalignr-3.c | 30 +++++++++++++++++++ .../gcc.target/i386/avx512vl-vpalignr-3.c | 30 +++++++++++++++++++ 5 files changed, 75 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-3.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-vpalignr-3.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1db6f919e9c..531ad4d6df1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2016-05-18 Jakub Jelinek + * config/i386/sse.md (_palignr): Use + constraint x instead of v in second alternative, add avx512bw + alternative. + * config/i386/sse.md (_pshufb3): Use constraint x instead of v in second alternative, add avx512bw alternative. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 63ecf861d5d..27796f4a62a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -14301,11 +14301,11 @@ (set_attr "mode" "")]) (define_insn "_palignr" - [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,v") + [(set (match_operand:SSESCALARMODE 0 "register_operand" "=x,x,v") (unspec:SSESCALARMODE - [(match_operand:SSESCALARMODE 1 "register_operand" "0,v") - (match_operand:SSESCALARMODE 2 "vector_operand" "xBm,vm") - (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")] + [(match_operand:SSESCALARMODE 1 "register_operand" "0,x,v") + (match_operand:SSESCALARMODE 2 "vector_operand" "xBm,xm,vm") + (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n,n")] UNSPEC_PALIGNR))] "TARGET_SSSE3" { @@ -14316,18 +14316,19 @@ case 0: return "palignr\t{%3, %2, %0|%0, %2, %3}"; case 1: + case 2: return "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}"; default: gcc_unreachable (); } } - [(set_attr "isa" "noavx,avx") + [(set_attr "isa" "noavx,avx,avx512bw") (set_attr "type" "sseishft") (set_attr "atom_unit" "sishuf") - (set_attr "prefix_data16" "1,*") + (set_attr "prefix_data16" "1,*,*") (set_attr "prefix_extra" "1") (set_attr "length_immediate" "1") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,vex,evex") (set_attr "mode" "")]) (define_insn "ssse3_palignrdi" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b528d8f4776..91c7ebcda1b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,5 +1,8 @@ 2016-05-18 Jakub Jelinek + * gcc.target/i386/avx512vl-vpalignr-3.c: New test. + * gcc.target/i386/avx512bw-vpalignr-3.c: New test. + * gcc.target/i386/avx512vl-vpshufb-3.c: New test. * gcc.target/i386/avx512bw-vpshufb-3.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-3.c b/gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-3.c new file mode 100644 index 00000000000..aacd4255bb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpalignr-3.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mavx512bw" } */ + +#include + +void +f1 (__m128i x, __m128i y) +{ + register __m128i a __asm ("xmm16"), b __asm ("xmm17"); + a = x; + b = y; + asm volatile ("" : "+v" (a), "+v" (b)); + a = _mm_alignr_epi8 (a, b, 3); + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler "vpalignr\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" } } */ + +void +f2 (__m256i x, __m256i y) +{ + register __m256i a __asm ("xmm16"), b __asm ("xmm17"); + a = x; + b = y; + asm volatile ("" : "+v" (a), "+v" (b)); + a = _mm256_alignr_epi8 (a, b, 3); + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler "vpalignr\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpalignr-3.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpalignr-3.c new file mode 100644 index 00000000000..7066d2af83b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpalignr-3.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */ + +#include + +void +f1 (__m128i x, __m128i y) +{ + register __m128i a __asm ("xmm16"), b __asm ("xmm17"); + a = x; + b = y; + asm volatile ("" : "+v" (a), "+v" (b)); + a = _mm_alignr_epi8 (a, b, 3); + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler-not "vpalignr\[^\n\r]*xmm1\[67]" } } */ + +void +f2 (__m256i x, __m256i y) +{ + register __m256i a __asm ("xmm16"), b __asm ("xmm17"); + a = x; + b = y; + asm volatile ("" : "+v" (a), "+v" (b)); + a = _mm256_alignr_epi8 (a, b, 3); + asm volatile ("" : "+v" (a)); +} + +/* { dg-final { scan-assembler-not "vpalignr\[^\n\r]*ymm1\[67]" } } */