aarch64: Add support for unpacked SVE MLA and MAD
This patch extends the MLA/MAD patterns to support unpacked integer vectors. The type suffix could be either the element size or the container size, but using the element size should be more efficient. gcc/ * config/aarch64/aarch64-sve.md (fma<mode>4): Extend from SVE_FULL_I to SVE_I. (@aarch64_pred_fma<mode>, cond_fma<mode>, *cond_fma<mode>_2) (*cond_fma<mode>_4, *cond_fma<mode>_any): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/mla_2.c: New test. * g++.target/aarch64/sve/cond_mla_1.C: Likewise. * g++.target/aarch64/sve/cond_mla_2.C: Likewise. * g++.target/aarch64/sve/cond_mla_3.C: Likewise. * g++.target/aarch64/sve/cond_mla_4.C: Likewise. * g++.target/aarch64/sve/cond_mla_5.C: Likewise.
This commit is contained in:
Richard Sandiford
parent
3ddc18251a
commit
cf7a335306
@ -6554,15 +6554,15 @@
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;; Unpredicated integer addition of product.
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(define_expand "fma<mode>4"
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[(set (match_operand:SVE_FULL_I 0 "register_operand")
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(plus:SVE_FULL_I
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand")
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(plus:SVE_I
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(unspec:SVE_I
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[(match_dup 4)
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(mult:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand")
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(match_operand:SVE_FULL_I 2 "nonmemory_operand"))]
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(mult:SVE_I
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(match_operand:SVE_I 1 "register_operand")
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(match_operand:SVE_I 2 "nonmemory_operand"))]
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UNSPEC_PRED_X)
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(match_operand:SVE_FULL_I 3 "register_operand")))]
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(match_operand:SVE_I 3 "register_operand")))]
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"TARGET_SVE"
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{
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if (aarch64_prepare_sve_int_fma (operands, PLUS))
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@ -6573,15 +6573,15 @@
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;; Predicated integer addition of product.
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(define_insn "@aarch64_pred_fma<mode>"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, ?&w")
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(plus:SVE_FULL_I
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w")
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(plus:SVE_I
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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(mult:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "%0, w, w")
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w, w"))]
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(mult:SVE_I
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(match_operand:SVE_I 2 "register_operand" "%0, w, w")
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(match_operand:SVE_I 3 "register_operand" "w, w, w"))]
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UNSPEC_PRED_X)
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(match_operand:SVE_FULL_I 4 "register_operand" "w, 0, w")))]
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(match_operand:SVE_I 4 "register_operand" "w, 0, w")))]
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"TARGET_SVE"
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"@
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mad\t%0.<Vetype>, %1/m, %3.<Vetype>, %4.<Vetype>
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@ -6592,15 +6592,15 @@
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;; Predicated integer addition of product with merging.
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(define_expand "cond_fma<mode>"
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[(set (match_operand:SVE_FULL_I 0 "register_operand")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand")
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(plus:SVE_FULL_I
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(mult:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand")
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(match_operand:SVE_FULL_I 3 "general_operand"))
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(match_operand:SVE_FULL_I 4 "register_operand"))
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(match_operand:SVE_FULL_I 5 "aarch64_simd_reg_or_zero")]
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(plus:SVE_I
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(mult:SVE_I
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(match_operand:SVE_I 2 "register_operand")
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(match_operand:SVE_I 3 "general_operand"))
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(match_operand:SVE_I 4 "register_operand"))
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(match_operand:SVE_I 5 "aarch64_simd_reg_or_zero")]
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UNSPEC_SEL))]
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"TARGET_SVE"
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{
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@ -6615,14 +6615,14 @@
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;; Predicated integer addition of product, merging with the first input.
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(define_insn "*cond_fma<mode>_2"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(plus:SVE_FULL_I
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(mult:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "0, w")
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w"))
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(match_operand:SVE_FULL_I 4 "register_operand" "w, w"))
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(plus:SVE_I
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(mult:SVE_I
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(match_operand:SVE_I 2 "register_operand" "0, w")
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(match_operand:SVE_I 3 "register_operand" "w, w"))
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(match_operand:SVE_I 4 "register_operand" "w, w"))
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(match_dup 2)]
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UNSPEC_SEL))]
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"TARGET_SVE"
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@ -6634,14 +6634,14 @@
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;; Predicated integer addition of product, merging with the third input.
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(define_insn "*cond_fma<mode>_4"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(plus:SVE_FULL_I
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(mult:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "w, w")
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w"))
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(match_operand:SVE_FULL_I 4 "register_operand" "0, w"))
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(plus:SVE_I
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(mult:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w, w")
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(match_operand:SVE_I 3 "register_operand" "w, w"))
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(match_operand:SVE_I 4 "register_operand" "0, w"))
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(match_dup 4)]
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UNSPEC_SEL))]
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"TARGET_SVE"
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@ -6653,15 +6653,15 @@
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;; Predicated integer addition of product, merging with an independent value.
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(define_insn_and_rewrite "*cond_fma<mode>_any"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, &w, &w, &w, &w, ?&w")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=&w, &w, &w, &w, &w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl")
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(plus:SVE_FULL_I
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(mult:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "w, w, 0, w, w, w")
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(match_operand:SVE_FULL_I 3 "register_operand" "w, w, w, 0, w, w"))
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(match_operand:SVE_FULL_I 4 "register_operand" "w, 0, w, w, w, w"))
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(match_operand:SVE_FULL_I 5 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, w")]
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(plus:SVE_I
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(mult:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w, w, 0, w, w, w")
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(match_operand:SVE_I 3 "register_operand" "w, w, w, 0, w, w"))
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(match_operand:SVE_I 4 "register_operand" "w, 0, w, w, w, w"))
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(match_operand:SVE_I 5 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, w")]
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UNSPEC_SEL))]
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"TARGET_SVE
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&& !rtx_equal_p (operands[2], operands[5])
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33
gcc/testsuite/g++.target/aarch64/sve/cond_mla_1.C
Normal file
33
gcc/testsuite/g++.target/aarch64/sve/cond_mla_1.C
Normal file
@ -0,0 +1,33 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c, TYPE d) \
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{ \
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return d == 0 ? a + b * c : a; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (uint32_t, 128)
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x0\][^L]*\tmla\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x0\][^L]*\tmla\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x0\][^L]*\tmla\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x0\][^L]*\tmla\t\1\.h,} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x0\][^L]*\tmla\t\1\.h,} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x0\][^L]*\tmla\t\1\.s,} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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33
gcc/testsuite/g++.target/aarch64/sve/cond_mla_2.C
Normal file
33
gcc/testsuite/g++.target/aarch64/sve/cond_mla_2.C
Normal file
@ -0,0 +1,33 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c, TYPE d) \
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{ \
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return d == 0 ? a + b * c : b; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (uint32_t, 128)
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x1\][^L]*\tmad\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x1\][^L]*\tmad\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x1\][^L]*\tmad\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x1\][^L]*\tmad\t\1\.h,} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x1\][^L]*\tmad\t\1\.h,} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x1\][^L]*\tmad\t\1\.s,} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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33
gcc/testsuite/g++.target/aarch64/sve/cond_mla_3.C
Normal file
33
gcc/testsuite/g++.target/aarch64/sve/cond_mla_3.C
Normal file
@ -0,0 +1,33 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O2 -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c, TYPE d) \
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{ \
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return d == 0 ? a + b * c : c; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (uint32_t, 128)
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x2\][^L]*\tmad\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x2\][^L]*\tmad\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x2\][^L]*\tmad\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x2\][^L]*\tmad\t\1\.h,} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x2\][^L]*\tmad\t\1\.h,} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2\][^L]*\tmad\t\1\.s,} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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36
gcc/testsuite/g++.target/aarch64/sve/cond_mla_4.C
Normal file
36
gcc/testsuite/g++.target/aarch64/sve/cond_mla_4.C
Normal file
@ -0,0 +1,36 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c, TYPE d) \
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{ \
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return d == 0 ? a + b * c : d; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (uint32_t, 128)
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.h, p[0-7]/z, \[x3\][^L]*\tmla\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.s, p[0-7]/z, \[x3\][^L]*\tmla\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[x3\][^L]*\tmla\t\1\.b,} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x3\][^L]*\tmla\t\1\.h,} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x3\][^L]*\tmla\t\1\.h,} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x3\][^L]*\tmla\t\1\.s,} } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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33
gcc/testsuite/g++.target/aarch64/sve/cond_mla_5.C
Normal file
33
gcc/testsuite/g++.target/aarch64/sve/cond_mla_5.C
Normal file
@ -0,0 +1,33 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP(TYPE) \
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TYPE \
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test##_##TYPE##_reg (TYPE a, TYPE b, TYPE c, TYPE d) \
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{ \
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return d == 0 ? a + b * c : 0; \
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}
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#define TEST_TYPE(TYPE, SIZE) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE)
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TEST_TYPE (uint8_t, 32)
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TEST_TYPE (uint8_t, 64)
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TEST_TYPE (uint16_t, 64)
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TEST_TYPE (uint8_t, 128)
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TEST_TYPE (uint16_t, 128)
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TEST_TYPE (uint32_t, 128)
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||||
|
||||
/* { dg-final { scan-assembler-times {\t(?:mla|mad)\tz[0-9]+\.b,} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\t(?:mla|mad)\tz[0-9]+\.h,} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\t(?:mla|mad)\tz[0-9]+\.s,} 1 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/z, z[0-9]+\.b\n} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z, z[0-9]+\.h\n} 2 } } */
|
||||
/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/z, z[0-9]+\.s\n} 1 } } */
|
||||
/* { dg-final { scan-assembler-not {\tsel\t} } } */
|
||||
34
gcc/testsuite/gcc.target/aarch64/sve/mla_2.c
Normal file
34
gcc/testsuite/gcc.target/aarch64/sve/mla_2.c
Normal file
@ -0,0 +1,34 @@
|
||||
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||
/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define TEST_OP(TYPE) \
|
||||
TYPE \
|
||||
test##_##TYPE##_##AMT (TYPE a, TYPE b, TYPE c) \
|
||||
{ \
|
||||
return a + b * c; \
|
||||
}
|
||||
|
||||
#define TEST_TYPE(TYPE, SIZE) \
|
||||
typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
|
||||
TEST_OP (TYPE##SIZE)
|
||||
|
||||
TEST_TYPE (int8_t, 32)
|
||||
TEST_TYPE (uint8_t, 32)
|
||||
|
||||
TEST_TYPE (int8_t, 64)
|
||||
TEST_TYPE (uint8_t, 64)
|
||||
TEST_TYPE (int16_t, 64)
|
||||
TEST_TYPE (uint16_t, 64)
|
||||
|
||||
TEST_TYPE (int8_t, 128)
|
||||
TEST_TYPE (uint8_t, 128)
|
||||
TEST_TYPE (int16_t, 128)
|
||||
TEST_TYPE (uint16_t, 128)
|
||||
TEST_TYPE (int32_t, 128)
|
||||
TEST_TYPE (uint32_t, 128)
|
||||
|
||||
/* { dg-final { scan-assembler-times {\t(?:mla|mad)\tz[0-9]+\.b,} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {\t(?:mla|mad)\tz[0-9]+\.h,} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\t(?:mla|mad)\tz[0-9]+\.s,} 2 } } */
|
||||
Loading…
Reference in New Issue
Block a user