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@ -202,11 +202,8 @@
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(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
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(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
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; Any hardware-supported floating-point mode
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; Any hardware-supported floating-point mode
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(define_mode_iterator FP [
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(define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
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(SF "TARGET_HARD_FLOAT
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(DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
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&& ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
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(DF "TARGET_HARD_FLOAT
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&& ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
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(TF "!TARGET_IEEEQUAD
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(TF "!TARGET_IEEEQUAD
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&& TARGET_HARD_FLOAT
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&& TARGET_HARD_FLOAT
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&& (TARGET_FPRS || TARGET_E500_DOUBLE)
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&& (TARGET_FPRS || TARGET_E500_DOUBLE)
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@ -5062,13 +5059,13 @@
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(define_expand "extendsfdf2"
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(define_expand "extendsfdf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "")
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[(set (match_operand:DF 0 "gpc_reg_operand" "")
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(float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
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(float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
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"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
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"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
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"")
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"")
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(define_insn_and_split "*extendsfdf2_fpr"
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(define_insn_and_split "*extendsfdf2_fpr"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
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(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
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(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
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"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"@
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"@
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#
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#
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fmr %0,%1
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fmr %0,%1
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@ -5084,53 +5081,53 @@
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(define_expand "truncdfsf2"
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(define_expand "truncdfsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
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(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
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"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
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"")
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"")
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(define_insn "*truncdfsf2_fpr"
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(define_insn "*truncdfsf2_fpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
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(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"frsp %0,%1"
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"frsp %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "aux_truncdfsf2"
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(define_insn "aux_truncdfsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
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"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frsp %0,%1"
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"frsp %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_expand "negsf2"
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(define_expand "negsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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(neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
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(neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
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"TARGET_HARD_FLOAT"
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"")
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"")
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(define_insn "*negsf2"
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(define_insn "*negsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
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(neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"fneg %0,%1"
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"fneg %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_expand "abssf2"
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(define_expand "abssf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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(abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
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(abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
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"TARGET_HARD_FLOAT"
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"")
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"")
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(define_insn "*abssf2"
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(define_insn "*abssf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
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(abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"fabs %0,%1"
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"fabs %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn ""
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(define_insn ""
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
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(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
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"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"TARGET_HARD_FLOAT && TARGET_FPRS"
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"fnabs %0,%1"
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"fnabs %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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@ -5138,14 +5135,14 @@
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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(plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
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(plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
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(match_operand:SF 2 "gpc_reg_operand" "")))]
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(match_operand:SF 2 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
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"TARGET_HARD_FLOAT"
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"")
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"")
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(define_insn ""
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(define_insn ""
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
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(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
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"fadds %0,%1,%2"
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"fadds %0,%1,%2"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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@ -5153,7 +5150,7 @@
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
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(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
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"{fa|fadd} %0,%1,%2"
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"{fa|fadd} %0,%1,%2"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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@ -5161,14 +5158,14 @@
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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(minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
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(minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
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(match_operand:SF 2 "gpc_reg_operand" "")))]
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(match_operand:SF 2 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
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"TARGET_HARD_FLOAT"
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"")
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"")
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(define_insn ""
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(define_insn ""
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
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(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
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"fsubs %0,%1,%2"
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"fsubs %0,%1,%2"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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@ -5176,7 +5173,7 @@
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
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(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
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"{fs|fsub} %0,%1,%2"
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"{fs|fsub} %0,%1,%2"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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@ -5184,14 +5181,14 @@
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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(mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
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(mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
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(match_operand:SF 2 "gpc_reg_operand" "")))]
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(match_operand:SF 2 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
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"TARGET_HARD_FLOAT"
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"")
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"")
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(define_insn ""
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(define_insn ""
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
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(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
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"fmuls %0,%1,%2"
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"fmuls %0,%1,%2"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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@ -5199,7 +5196,7 @@
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
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(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
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"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
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"{fm|fmul} %0,%1,%2"
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"{fm|fmul} %0,%1,%2"
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[(set_attr "type" "dmul")])
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[(set_attr "type" "dmul")])
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@ -5207,15 +5204,14 @@
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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|
(div:SF (match_operand:SF 1 "gpc_reg_operand" "")
|
|
|
|
(div:SF (match_operand:SF 1 "gpc_reg_operand" "")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "")))]
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
|
|
|
|
"TARGET_HARD_FLOAT"
|
|
|
|
"")
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
(define_insn ""
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
|
|
|
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
|
|
|
|
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
&& TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
|
|
|
|
|
|
|
|
"fdivs %0,%1,%2"
|
|
|
|
"fdivs %0,%1,%2"
|
|
|
|
[(set_attr "type" "sdiv")])
|
|
|
|
[(set_attr "type" "sdiv")])
|
|
|
|
|
|
|
|
|
|
|
@ -5223,8 +5219,7 @@
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
|
|
|
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
|
|
|
|
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f")))]
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
&& TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
|
|
|
|
|
|
|
|
"{fd|fdiv} %0,%1,%2"
|
|
|
|
"{fd|fdiv} %0,%1,%2"
|
|
|
|
[(set_attr "type" "ddiv")])
|
|
|
|
[(set_attr "type" "ddiv")])
|
|
|
|
|
|
|
|
|
|
|
@ -5252,8 +5247,7 @@
|
|
|
|
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
|
|
|
|
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
|
|
|
|
|
|
|
|
"fmadds %0,%1,%2,%3"
|
|
|
|
"fmadds %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -5262,8 +5256,7 @@
|
|
|
|
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
|
|
|
|
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
|
|
|
|
|
|
|
|
"{fma|fmadd} %0,%1,%2,%3"
|
|
|
|
"{fma|fmadd} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
|
|
|
|
|
|
|
@ -5272,8 +5265,7 @@
|
|
|
|
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
|
|
|
|
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
|
|
|
|
|
|
|
|
"fmsubs %0,%1,%2,%3"
|
|
|
|
"fmsubs %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -5282,8 +5274,7 @@
|
|
|
|
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
|
|
|
|
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
|
|
|
|
|
|
|
|
"{fms|fmsub} %0,%1,%2,%3"
|
|
|
|
"{fms|fmsub} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
|
|
|
|
|
|
|
@ -5293,7 +5284,7 @@
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
&& TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
&& HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
"fnmadds %0,%1,%2,%3"
|
|
|
|
"fnmadds %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -5302,7 +5293,7 @@
|
|
|
|
(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
|
|
|
|
(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
&& ! HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
&& ! HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
"fnmadds %0,%1,%2,%3"
|
|
|
|
"fnmadds %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
@ -5312,8 +5303,7 @@
|
|
|
|
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
|
|
|
|
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
|
|
|
|
|
|
|
|
"{fnma|fnmadd} %0,%1,%2,%3"
|
|
|
|
"{fnma|fnmadd} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
|
|
|
|
|
|
|
@ -5323,7 +5313,7 @@
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
&& TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
&& ! HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
"{fnma|fnmadd} %0,%1,%2,%3"
|
|
|
|
"{fnma|fnmadd} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
|
|
|
|
|
|
|
@ -5333,7 +5323,7 @@
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
&& TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
&& HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
"fnmsubs %0,%1,%2,%3"
|
|
|
|
"fnmsubs %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -5343,7 +5333,7 @@
|
|
|
|
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))))]
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))))]
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
&& TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
&& ! HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
"fnmsubs %0,%1,%2,%3"
|
|
|
|
"fnmsubs %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -5352,8 +5342,7 @@
|
|
|
|
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
|
|
|
|
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
|
|
|
|
|
|
|
|
"{fnms|fnmsub} %0,%1,%2,%3"
|
|
|
|
"{fnms|fnmsub} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
|
|
|
|
|
|
|
@ -5363,31 +5352,27 @@
|
|
|
|
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))))]
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f"))))]
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
&& TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
&& ! HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
"{fnms|fnmsub} %0,%1,%2,%3"
|
|
|
|
"{fnms|fnmsub} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
|
|
|
|
|
|
|
|
(define_expand "sqrtsf2"
|
|
|
|
(define_expand "sqrtsf2"
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "")
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "")
|
|
|
|
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
|
|
|
|
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
|
|
|
|
"(TARGET_PPC_GPOPT || TARGET_POWER2)
|
|
|
|
"(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
|
|
|
|
|
|
|
|
&& !TARGET_SIMPLE_FPU"
|
|
|
|
|
|
|
|
"")
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
(define_insn ""
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
|
|
|
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
|
|
|
|
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_PPC_GPOPT && TARGET_HARD_FLOAT
|
|
|
|
"TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
&& TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
|
|
|
|
|
|
|
|
"fsqrts %0,%1"
|
|
|
|
"fsqrts %0,%1"
|
|
|
|
[(set_attr "type" "ssqrt")])
|
|
|
|
[(set_attr "type" "ssqrt")])
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn ""
|
|
|
|
(define_insn ""
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
|
|
|
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
|
|
|
|
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
&& TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
|
|
|
|
|
|
|
|
"fsqrt %0,%1"
|
|
|
|
"fsqrt %0,%1"
|
|
|
|
[(set_attr "type" "dsqrt")])
|
|
|
|
[(set_attr "type" "dsqrt")])
|
|
|
|
|
|
|
|
|
|
|
@ -5420,7 +5405,7 @@
|
|
|
|
(match_dup 5))
|
|
|
|
(match_dup 5))
|
|
|
|
(match_dup 3)
|
|
|
|
(match_dup 3)
|
|
|
|
(match_dup 4)))]
|
|
|
|
(match_dup 4)))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
&& !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
&& !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
|
|
|
|
{
|
|
|
|
{
|
|
|
|
operands[3] = gen_reg_rtx (SFmode);
|
|
|
|
operands[3] = gen_reg_rtx (SFmode);
|
|
|
@ -5438,7 +5423,7 @@
|
|
|
|
(match_dup 5))
|
|
|
|
(match_dup 5))
|
|
|
|
(match_dup 3)
|
|
|
|
(match_dup 3)
|
|
|
|
(match_dup 4)))]
|
|
|
|
(match_dup 4)))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
&& !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
|
|
|
|
&& !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
|
|
|
|
{
|
|
|
|
{
|
|
|
|
operands[3] = gen_reg_rtx (DFmode);
|
|
|
|
operands[3] = gen_reg_rtx (DFmode);
|
|
|
@ -5456,8 +5441,7 @@
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" ""))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" ""))
|
|
|
|
(match_dup 1)
|
|
|
|
(match_dup 1)
|
|
|
|
(match_dup 2)))]
|
|
|
|
(match_dup 2)))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
|
|
|
|
&& TARGET_SINGLE_FLOAT && !flag_trapping_math"
|
|
|
|
|
|
|
|
"{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
|
|
|
|
"{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
|
|
|
|
|
|
|
|
|
|
|
|
(define_expand "sminsf3"
|
|
|
|
(define_expand "sminsf3"
|
|
|
@ -5466,8 +5450,7 @@
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" ""))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" ""))
|
|
|
|
(match_dup 2)
|
|
|
|
(match_dup 2)
|
|
|
|
(match_dup 1)))]
|
|
|
|
(match_dup 1)))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
|
|
|
|
&& TARGET_SINGLE_FLOAT && !flag_trapping_math"
|
|
|
|
|
|
|
|
"{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
|
|
|
|
"{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
|
|
|
|
|
|
|
|
|
|
|
|
(define_split
|
|
|
|
(define_split
|
|
|
@ -5475,8 +5458,7 @@
|
|
|
|
(match_operator:SF 3 "min_max_operator"
|
|
|
|
(match_operator:SF 3 "min_max_operator"
|
|
|
|
[(match_operand:SF 1 "gpc_reg_operand" "")
|
|
|
|
[(match_operand:SF 1 "gpc_reg_operand" "")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "")]))]
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "")]))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
|
|
|
|
&& TARGET_SINGLE_FLOAT && !flag_trapping_math"
|
|
|
|
|
|
|
|
[(const_int 0)]
|
|
|
|
[(const_int 0)]
|
|
|
|
"
|
|
|
|
"
|
|
|
|
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
|
|
|
|
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
|
|
|
@ -5537,7 +5519,7 @@
|
|
|
|
(if_then_else:SF (match_operand 1 "comparison_operator" "")
|
|
|
|
(if_then_else:SF (match_operand 1 "comparison_operator" "")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "")
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "")))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"
|
|
|
|
"
|
|
|
|
{
|
|
|
|
{
|
|
|
|
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
|
|
|
|
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
|
|
|
@ -5552,7 +5534,7 @@
|
|
|
|
(match_operand:SF 4 "zero_fp_constant" "F"))
|
|
|
|
(match_operand:SF 4 "zero_fp_constant" "F"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"fsel %0,%1,%2,%3"
|
|
|
|
"fsel %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -5562,40 +5544,40 @@
|
|
|
|
(match_operand:DF 4 "zero_fp_constant" "F"))
|
|
|
|
(match_operand:DF 4 "zero_fp_constant" "F"))
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"fsel %0,%1,%2,%3"
|
|
|
|
"fsel %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
|
(define_expand "negdf2"
|
|
|
|
(define_expand "negdf2"
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
|
|
|
|
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
|
|
|
|
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
|
|
|
|
"")
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn "*negdf2_fpr"
|
|
|
|
(define_insn "*negdf2_fpr"
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
|
|
|
|
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"fneg %0,%1"
|
|
|
|
"fneg %0,%1"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
|
(define_expand "absdf2"
|
|
|
|
(define_expand "absdf2"
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
|
|
|
|
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
|
|
|
|
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
|
|
|
|
"")
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn "*absdf2_fpr"
|
|
|
|
(define_insn "*absdf2_fpr"
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
|
|
|
|
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"fabs %0,%1"
|
|
|
|
"fabs %0,%1"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn "*nabsdf2_fpr"
|
|
|
|
(define_insn "*nabsdf2_fpr"
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
|
|
|
|
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"fnabs %0,%1"
|
|
|
|
"fnabs %0,%1"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -5603,14 +5585,14 @@
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
|
|
|
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
|
|
|
|
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
|
|
|
|
"")
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn "*adddf3_fpr"
|
|
|
|
(define_insn "*adddf3_fpr"
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"{fa|fadd} %0,%1,%2"
|
|
|
|
"{fa|fadd} %0,%1,%2"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -5618,14 +5600,14 @@
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
|
|
|
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
|
|
|
|
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
|
|
|
|
"")
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn "*subdf3_fpr"
|
|
|
|
(define_insn "*subdf3_fpr"
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
|
|
|
|
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"{fs|fsub} %0,%1,%2"
|
|
|
|
"{fs|fsub} %0,%1,%2"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -5633,14 +5615,14 @@
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
|
|
|
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
|
|
|
|
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
|
|
|
|
"")
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn "*muldf3_fpr"
|
|
|
|
(define_insn "*muldf3_fpr"
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"{fm|fmul} %0,%1,%2"
|
|
|
|
"{fm|fmul} %0,%1,%2"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
|
|
|
|
|
|
|
@ -5648,14 +5630,14 @@
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
|
|
|
(div:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
|
|
|
(div:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE) && !TARGET_SIMPLE_FPU"
|
|
|
|
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
|
|
|
|
"")
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
|
|
(define_insn "*divdf3_fpr"
|
|
|
|
(define_insn "*divdf3_fpr"
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
|
|
|
|
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"{fd|fdiv} %0,%1,%2"
|
|
|
|
"{fd|fdiv} %0,%1,%2"
|
|
|
|
[(set_attr "type" "ddiv")])
|
|
|
|
[(set_attr "type" "ddiv")])
|
|
|
|
|
|
|
|
|
|
|
@ -5683,7 +5665,7 @@
|
|
|
|
(plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
|
|
|
|
"{fma|fmadd} %0,%1,%2,%3"
|
|
|
|
"{fma|fmadd} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
|
|
|
|
|
|
|
@ -5692,7 +5674,7 @@
|
|
|
|
(minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
|
|
|
|
"{fms|fmsub} %0,%1,%2,%3"
|
|
|
|
"{fms|fmsub} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
|
|
|
|
|
|
|
@ -5701,7 +5683,7 @@
|
|
|
|
(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
&& HONOR_SIGNED_ZEROS (DFmode)"
|
|
|
|
&& HONOR_SIGNED_ZEROS (DFmode)"
|
|
|
|
"{fnma|fnmadd} %0,%1,%2,%3"
|
|
|
|
"{fnma|fnmadd} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
@ -5711,7 +5693,7 @@
|
|
|
|
(minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
|
|
|
|
(minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
&& ! HONOR_SIGNED_ZEROS (DFmode)"
|
|
|
|
&& ! HONOR_SIGNED_ZEROS (DFmode)"
|
|
|
|
"{fnma|fnmadd} %0,%1,%2,%3"
|
|
|
|
"{fnma|fnmadd} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
@ -5721,7 +5703,7 @@
|
|
|
|
(neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f"))))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
&& HONOR_SIGNED_ZEROS (DFmode)"
|
|
|
|
&& HONOR_SIGNED_ZEROS (DFmode)"
|
|
|
|
"{fnms|fnmsub} %0,%1,%2,%3"
|
|
|
|
"{fnms|fnmsub} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
@ -5731,7 +5713,7 @@
|
|
|
|
(minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
|
|
|
|
(minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
|
|
|
|
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f"))))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
|
|
|
|
&& ! HONOR_SIGNED_ZEROS (DFmode)"
|
|
|
|
&& ! HONOR_SIGNED_ZEROS (DFmode)"
|
|
|
|
"{fnms|fnmsub} %0,%1,%2,%3"
|
|
|
|
"{fnms|fnmsub} %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
|
[(set_attr "type" "dmul")])
|
|
|
@ -5739,8 +5721,7 @@
|
|
|
|
(define_insn "sqrtdf2"
|
|
|
|
(define_insn "sqrtdf2"
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
|
|
|
|
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
|
|
|
|
"(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
&& TARGET_DOUBLE_FLOAT"
|
|
|
|
|
|
|
|
"fsqrt %0,%1"
|
|
|
|
"fsqrt %0,%1"
|
|
|
|
[(set_attr "type" "dsqrt")])
|
|
|
|
[(set_attr "type" "dsqrt")])
|
|
|
|
|
|
|
|
|
|
|
@ -5753,8 +5734,7 @@
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" ""))
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" ""))
|
|
|
|
(match_dup 1)
|
|
|
|
(match_dup 1)
|
|
|
|
(match_dup 2)))]
|
|
|
|
(match_dup 2)))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
|
|
|
|
&& !flag_trapping_math"
|
|
|
|
|
|
|
|
"{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
|
|
|
|
"{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
|
|
|
|
|
|
|
|
|
|
|
|
(define_expand "smindf3"
|
|
|
|
(define_expand "smindf3"
|
|
|
@ -5763,8 +5743,7 @@
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" ""))
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" ""))
|
|
|
|
(match_dup 2)
|
|
|
|
(match_dup 2)
|
|
|
|
(match_dup 1)))]
|
|
|
|
(match_dup 1)))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
|
|
|
|
&& !flag_trapping_math"
|
|
|
|
|
|
|
|
"{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
|
|
|
|
"{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
|
|
|
|
|
|
|
|
|
|
|
|
(define_split
|
|
|
|
(define_split
|
|
|
@ -5772,8 +5751,7 @@
|
|
|
|
(match_operator:DF 3 "min_max_operator"
|
|
|
|
(match_operator:DF 3 "min_max_operator"
|
|
|
|
[(match_operand:DF 1 "gpc_reg_operand" "")
|
|
|
|
[(match_operand:DF 1 "gpc_reg_operand" "")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")]))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")]))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
|
|
|
|
&& !flag_trapping_math"
|
|
|
|
|
|
|
|
[(const_int 0)]
|
|
|
|
[(const_int 0)]
|
|
|
|
"
|
|
|
|
"
|
|
|
|
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
|
|
|
|
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
|
|
|
@ -5786,7 +5764,7 @@
|
|
|
|
(if_then_else:DF (match_operand 1 "comparison_operator" "")
|
|
|
|
(if_then_else:DF (match_operand 1 "comparison_operator" "")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "")
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "")))]
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"
|
|
|
|
"
|
|
|
|
{
|
|
|
|
{
|
|
|
|
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
|
|
|
|
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
|
|
|
@ -5801,7 +5779,7 @@
|
|
|
|
(match_operand:DF 4 "zero_fp_constant" "F"))
|
|
|
|
(match_operand:DF 4 "zero_fp_constant" "F"))
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"fsel %0,%1,%2,%3"
|
|
|
|
"fsel %0,%1,%2,%3"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -5820,13 +5798,13 @@
|
|
|
|
(define_expand "fixuns_truncsfsi2"
|
|
|
|
(define_expand "fixuns_truncsfsi2"
|
|
|
|
[(set (match_operand:SI 0 "gpc_reg_operand" "")
|
|
|
|
[(set (match_operand:SI 0 "gpc_reg_operand" "")
|
|
|
|
(unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
|
|
|
|
(unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && !TARGET_FPRS"
|
|
|
|
"")
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
|
|
(define_expand "fix_truncsfsi2"
|
|
|
|
(define_expand "fix_truncsfsi2"
|
|
|
|
[(set (match_operand:SI 0 "gpc_reg_operand" "")
|
|
|
|
[(set (match_operand:SI 0 "gpc_reg_operand" "")
|
|
|
|
(fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
|
|
|
|
(fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && !TARGET_FPRS"
|
|
|
|
"")
|
|
|
|
"")
|
|
|
|
|
|
|
|
|
|
|
|
; For each of these conversions, there is a define_expand, a define_insn
|
|
|
|
; For each of these conversions, there is a define_expand, a define_insn
|
|
|
@ -5842,8 +5820,7 @@
|
|
|
|
(clobber (match_dup 4))
|
|
|
|
(clobber (match_dup 4))
|
|
|
|
(clobber (match_dup 5))
|
|
|
|
(clobber (match_dup 5))
|
|
|
|
(clobber (match_dup 6))])]
|
|
|
|
(clobber (match_dup 6))])]
|
|
|
|
"TARGET_HARD_FLOAT
|
|
|
|
"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
|
|
|
|
&& ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
|
|
|
|
|
|
|
|
"
|
|
|
|
"
|
|
|
|
{
|
|
|
|
{
|
|
|
|
if (TARGET_E500_DOUBLE)
|
|
|
|
if (TARGET_E500_DOUBLE)
|
|
|
@ -5873,7 +5850,7 @@
|
|
|
|
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
|
|
|
|
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
|
|
|
|
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
|
|
|
|
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
|
|
|
|
(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
|
|
|
|
(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
|
|
|
|
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"#"
|
|
|
|
"#"
|
|
|
|
"&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
|
|
|
|
"&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
|
|
|
|
[(pc)]
|
|
|
|
[(pc)]
|
|
|
@ -5902,7 +5879,7 @@
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(define_expand "floatunssisf2"
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(define_expand "floatunssisf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
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(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"")
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"")
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(define_expand "floatunssidf2"
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(define_expand "floatunssidf2"
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@ -5912,7 +5889,7 @@
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(use (match_dup 3))
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(use (match_dup 3))
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(clobber (match_dup 4))
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(clobber (match_dup 4))
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(clobber (match_dup 5))])]
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(clobber (match_dup 5))])]
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"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
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"TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
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"
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"
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{
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{
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if (TARGET_E500_DOUBLE)
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if (TARGET_E500_DOUBLE)
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@ -5940,7 +5917,7 @@
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(use (match_operand:DF 3 "gpc_reg_operand" "f"))
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(use (match_operand:DF 3 "gpc_reg_operand" "f"))
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(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
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(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
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(clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
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(clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
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"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
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"#"
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"#"
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"&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
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"&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
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[(pc)]
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[(pc)]
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@ -5970,7 +5947,7 @@
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(clobber (match_dup 2))
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(clobber (match_dup 2))
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(clobber (match_dup 3))])]
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(clobber (match_dup 3))])]
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"(TARGET_POWER2 || TARGET_POWERPC)
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"(TARGET_POWER2 || TARGET_POWERPC)
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&& TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
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&& TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
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"
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"
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{
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{
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if (TARGET_E500_DOUBLE)
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if (TARGET_E500_DOUBLE)
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@ -6006,8 +5983,7 @@
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
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(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
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(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
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&& TARGET_DOUBLE_FLOAT"
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"#"
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"#"
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"&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
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"&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
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[(pc)]
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[(pc)]
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@ -6029,7 +6005,6 @@
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
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&& TARGET_DOUBLE_FLOAT
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&& TARGET_PPC_GFXOPT"
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&& TARGET_PPC_GFXOPT"
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"#"
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"#"
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"&& 1"
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"&& 1"
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@ -6047,8 +6022,7 @@
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
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(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
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(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
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(clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
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(clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
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"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
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"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
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&& TARGET_DOUBLE_FLOAT"
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"#"
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"#"
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"&& 1"
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"&& 1"
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[(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
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[(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
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@ -6065,64 +6039,63 @@
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[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
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[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
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(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
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(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
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UNSPEC_FCTIWZ))]
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UNSPEC_FCTIWZ))]
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
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"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
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&& TARGET_DOUBLE_FLOAT"
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"{fcirz|fctiwz} %0,%1"
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"{fcirz|fctiwz} %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "btruncdf2"
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(define_insn "btruncdf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"friz %0,%1"
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"friz %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "btruncsf2"
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(define_insn "btruncsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"friz %0,%1"
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"friz %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "ceildf2"
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(define_insn "ceildf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frip %0,%1"
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"frip %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "ceilsf2"
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(define_insn "ceilsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frip %0,%1"
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"frip %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "floordf2"
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(define_insn "floordf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frim %0,%1"
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"frim %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "floorsf2"
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(define_insn "floorsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frim %0,%1"
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"frim %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "rounddf2"
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(define_insn "rounddf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
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(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frin %0,%1"
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"frin %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "roundsf2"
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(define_insn "roundsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
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(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
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"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
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"frin %0,%1"
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"frin %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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@ -6138,27 +6111,27 @@
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(define_expand "floatsisf2"
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(define_expand "floatsisf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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(float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
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(float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
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"TARGET_HARD_FLOAT && (!TARGET_FPRS || TARGET_SINGLE_FPU)"
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"TARGET_HARD_FLOAT && !TARGET_FPRS"
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"")
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"")
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(define_insn "floatdidf2"
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(define_insn "floatdidf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
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(float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
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"fcfid %0,%1"
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"fcfid %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_insn "fix_truncdfdi2"
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(define_insn "fix_truncdfdi2"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
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[(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
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(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
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(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
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"fctidz %0,%1"
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"fctidz %0,%1"
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[(set_attr "type" "fp")])
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[(set_attr "type" "fp")])
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(define_expand "floatdisf2"
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(define_expand "floatdisf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "")
|
|
|
|
(float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
|
|
|
|
(float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
|
|
|
|
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
|
|
|
|
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"
|
|
|
|
"
|
|
|
|
{
|
|
|
|
{
|
|
|
|
rtx val = operands[1];
|
|
|
|
rtx val = operands[1];
|
|
|
@ -6180,7 +6153,7 @@
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
|
|
|
(float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
|
|
|
|
(float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
|
|
|
|
(clobber (match_scratch:DF 2 "=f"))]
|
|
|
|
(clobber (match_scratch:DF 2 "=f"))]
|
|
|
|
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
|
|
|
|
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"#"
|
|
|
|
"#"
|
|
|
|
"&& reload_completed"
|
|
|
|
"&& reload_completed"
|
|
|
|
[(set (match_dup 2)
|
|
|
|
[(set (match_dup 2)
|
|
|
@ -6214,7 +6187,7 @@
|
|
|
|
(label_ref (match_operand:DI 2 "" ""))
|
|
|
|
(label_ref (match_operand:DI 2 "" ""))
|
|
|
|
(pc)))
|
|
|
|
(pc)))
|
|
|
|
(set (match_dup 0) (match_dup 1))]
|
|
|
|
(set (match_dup 0) (match_dup 1))]
|
|
|
|
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
|
|
|
|
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"
|
|
|
|
"
|
|
|
|
{
|
|
|
|
{
|
|
|
|
operands[3] = gen_reg_rtx (DImode);
|
|
|
|
operands[3] = gen_reg_rtx (DImode);
|
|
|
@ -8246,7 +8219,7 @@
|
|
|
|
(match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
|
|
|
|
(match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
|
|
|
|
"(gpc_reg_operand (operands[0], SFmode)
|
|
|
|
"(gpc_reg_operand (operands[0], SFmode)
|
|
|
|
|| gpc_reg_operand (operands[1], SFmode))
|
|
|
|
|| gpc_reg_operand (operands[1], SFmode))
|
|
|
|
&& (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
|
|
|
|
&& (TARGET_HARD_FLOAT && TARGET_FPRS)"
|
|
|
|
"@
|
|
|
|
"@
|
|
|
|
mr %0,%1
|
|
|
|
mr %0,%1
|
|
|
|
{l%U1%X1|lwz%U1%X1} %0,%1
|
|
|
|
{l%U1%X1|lwz%U1%X1} %0,%1
|
|
|
@ -8384,7 +8357,7 @@
|
|
|
|
(define_insn "*movdf_hardfloat32"
|
|
|
|
(define_insn "*movdf_hardfloat32"
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
|
|
|
|
(match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
|
|
|
|
(match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
|
|
|
|
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
|
|
|
|
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
&& (gpc_reg_operand (operands[0], DFmode)
|
|
|
|
&& (gpc_reg_operand (operands[0], DFmode)
|
|
|
|
|| gpc_reg_operand (operands[1], DFmode))"
|
|
|
|
|| gpc_reg_operand (operands[1], DFmode))"
|
|
|
|
"*
|
|
|
|
"*
|
|
|
@ -8479,9 +8452,7 @@
|
|
|
|
(define_insn "*movdf_softfloat32"
|
|
|
|
(define_insn "*movdf_softfloat32"
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
|
|
|
|
(match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
|
|
|
|
(match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
|
|
|
|
"! TARGET_POWERPC64
|
|
|
|
"! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
|
|
|
|
&& ((TARGET_FPRS && !TARGET_DOUBLE_FLOAT)
|
|
|
|
|
|
|
|
|| TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
|
|
|
|
|
|
|
|
&& (gpc_reg_operand (operands[0], DFmode)
|
|
|
|
&& (gpc_reg_operand (operands[0], DFmode)
|
|
|
|
|| gpc_reg_operand (operands[1], DFmode))"
|
|
|
|
|| gpc_reg_operand (operands[1], DFmode))"
|
|
|
|
"*
|
|
|
|
"*
|
|
|
@ -8525,7 +8496,6 @@
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
|
|
|
|
(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
|
|
|
|
(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
|
|
|
|
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
&& TARGET_DOUBLE_FLOAT
|
|
|
|
|
|
|
|
&& (gpc_reg_operand (operands[0], DFmode)
|
|
|
|
&& (gpc_reg_operand (operands[0], DFmode)
|
|
|
|
|| gpc_reg_operand (operands[1], DFmode))"
|
|
|
|
|| gpc_reg_operand (operands[1], DFmode))"
|
|
|
|
"@
|
|
|
|
"@
|
|
|
@ -8552,7 +8522,6 @@
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
|
|
|
|
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
|
|
|
|
(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
|
|
|
|
(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
|
|
|
|
"TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
"TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
|
|
|
|
&& TARGET_DOUBLE_FLOAT
|
|
|
|
|
|
|
|
&& (gpc_reg_operand (operands[0], DFmode)
|
|
|
|
&& (gpc_reg_operand (operands[0], DFmode)
|
|
|
|
|| gpc_reg_operand (operands[1], DFmode))"
|
|
|
|
|| gpc_reg_operand (operands[1], DFmode))"
|
|
|
|
"@
|
|
|
|
"@
|
|
|
@ -8645,8 +8614,7 @@
|
|
|
|
(float_extend:TF (match_operand:DF 1 "input_operand" "")))
|
|
|
|
(float_extend:TF (match_operand:DF 1 "input_operand" "")))
|
|
|
|
(use (match_dup 2))])]
|
|
|
|
(use (match_dup 2))])]
|
|
|
|
"!TARGET_IEEEQUAD
|
|
|
|
"!TARGET_IEEEQUAD
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
|
|
|
|
&& TARGET_LONG_DOUBLE_128"
|
|
|
|
|
|
|
|
{
|
|
|
|
{
|
|
|
|
operands[2] = CONST0_RTX (DFmode);
|
|
|
|
operands[2] = CONST0_RTX (DFmode);
|
|
|
|
/* Generate GOT reference early for SVR4 PIC. */
|
|
|
|
/* Generate GOT reference early for SVR4 PIC. */
|
|
|
@ -8659,8 +8627,7 @@
|
|
|
|
(float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
|
|
|
|
(float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
|
|
|
|
(use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
|
|
|
|
(use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
|
|
|
|
"!TARGET_IEEEQUAD
|
|
|
|
"!TARGET_IEEEQUAD
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
|
|
|
|
&& TARGET_LONG_DOUBLE_128"
|
|
|
|
|
|
|
|
"#"
|
|
|
|
"#"
|
|
|
|
"&& reload_completed"
|
|
|
|
"&& reload_completed"
|
|
|
|
[(pc)]
|
|
|
|
[(pc)]
|
|
|
@ -8717,8 +8684,7 @@
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
|
|
|
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
|
|
|
|
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
|
|
|
|
"!TARGET_IEEEQUAD && TARGET_XL_COMPAT
|
|
|
|
"!TARGET_IEEEQUAD && TARGET_XL_COMPAT
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
|
|
|
|
&& TARGET_LONG_DOUBLE_128"
|
|
|
|
|
|
|
|
"fadd %0,%1,%L1"
|
|
|
|
"fadd %0,%1,%L1"
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
[(set_attr "type" "fp")])
|
|
|
|
|
|
|
|
|
|
|
@ -8742,8 +8708,7 @@
|
|
|
|
(float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
|
|
|
|
(float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
|
|
|
|
(clobber (match_scratch:DF 2 "=f"))]
|
|
|
|
(clobber (match_scratch:DF 2 "=f"))]
|
|
|
|
"!TARGET_IEEEQUAD
|
|
|
|
"!TARGET_IEEEQUAD
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
|
|
|
|
&& TARGET_LONG_DOUBLE_128"
|
|
|
|
|
|
|
|
"#"
|
|
|
|
"#"
|
|
|
|
"&& reload_completed"
|
|
|
|
"&& reload_completed"
|
|
|
|
[(set (match_dup 2)
|
|
|
|
[(set (match_dup 2)
|
|
|
@ -8773,7 +8738,7 @@
|
|
|
|
(unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
|
|
|
|
(unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
|
|
|
|
UNSPEC_FIX_TRUNC_TF))
|
|
|
|
UNSPEC_FIX_TRUNC_TF))
|
|
|
|
(clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
|
|
|
|
(clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
|
|
|
|
"mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
|
|
|
|
[(set_attr "type" "fp")
|
|
|
|
[(set_attr "type" "fp")
|
|
|
|
(set_attr "length" "20")])
|
|
|
|
(set_attr "length" "20")])
|
|
|
@ -8894,8 +8859,7 @@
|
|
|
|
(pc)))
|
|
|
|
(pc)))
|
|
|
|
(set (match_dup 6) (neg:DF (match_dup 6)))]
|
|
|
|
(set (match_dup 6) (neg:DF (match_dup 6)))]
|
|
|
|
"!TARGET_IEEEQUAD
|
|
|
|
"!TARGET_IEEEQUAD
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
|
|
|
|
&& TARGET_LONG_DOUBLE_128"
|
|
|
|
|
|
|
|
"
|
|
|
|
"
|
|
|
|
{
|
|
|
|
{
|
|
|
|
const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
|
|
|
|
const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
|
|
|
@ -10046,7 +10010,7 @@
|
|
|
|
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
|
|
|
|
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
|
|
|
|
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
|
|
|
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
|
|
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
|
|
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
|
|
|
|
"@
|
|
|
|
"@
|
|
|
|
lfsux %3,%0,%2
|
|
|
|
lfsux %3,%0,%2
|
|
|
|
lfsu %3,%2(%0)"
|
|
|
|
lfsu %3,%2(%0)"
|
|
|
@ -10058,7 +10022,7 @@
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f,f"))
|
|
|
|
(match_operand:SF 3 "gpc_reg_operand" "f,f"))
|
|
|
|
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
|
|
|
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
|
|
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
|
|
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
|
|
|
|
"@
|
|
|
|
"@
|
|
|
|
stfsux %3,%0,%2
|
|
|
|
stfsux %3,%0,%2
|
|
|
|
stfsu %3,%2(%0)"
|
|
|
|
stfsu %3,%2(%0)"
|
|
|
@ -10094,7 +10058,7 @@
|
|
|
|
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
|
|
|
|
(match_operand:SI 2 "reg_or_short_operand" "r,I"))))
|
|
|
|
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
|
|
|
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
|
|
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
|
|
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
|
|
|
|
"@
|
|
|
|
"@
|
|
|
|
lfdux %3,%0,%2
|
|
|
|
lfdux %3,%0,%2
|
|
|
|
lfdu %3,%2(%0)"
|
|
|
|
lfdu %3,%2(%0)"
|
|
|
@ -10106,7 +10070,7 @@
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f,f"))
|
|
|
|
(match_operand:DF 3 "gpc_reg_operand" "f,f"))
|
|
|
|
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
|
|
|
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
|
|
|
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
|
|
|
(plus:SI (match_dup 1) (match_dup 2)))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
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"@
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"@
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stfdux %3,%0,%2
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stfdux %3,%0,%2
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stfdu %3,%2(%0)"
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stfdu %3,%2(%0)"
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@ -10127,7 +10091,7 @@
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(set (match_operand:DF 2 "gpc_reg_operand" "")
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(set (match_operand:DF 2 "gpc_reg_operand" "")
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(match_operand:DF 3 "memory_operand" ""))]
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(match_operand:DF 3 "memory_operand" ""))]
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"TARGET_POWER2
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"TARGET_POWER2
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&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
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&& TARGET_HARD_FLOAT && TARGET_FPRS
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&& registers_ok_for_quad_peep (operands[0], operands[2])
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&& registers_ok_for_quad_peep (operands[0], operands[2])
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&& mems_ok_for_quad_peep (operands[1], operands[3])"
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&& mems_ok_for_quad_peep (operands[1], operands[3])"
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[(set (match_dup 0)
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[(set (match_dup 0)
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@ -10149,7 +10113,7 @@
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(set (match_operand:DF 2 "memory_operand" "")
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(set (match_operand:DF 2 "memory_operand" "")
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(match_operand:DF 3 "gpc_reg_operand" ""))]
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(match_operand:DF 3 "gpc_reg_operand" ""))]
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"TARGET_POWER2
|
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"TARGET_POWER2
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&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
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&& TARGET_HARD_FLOAT && TARGET_FPRS
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&& registers_ok_for_quad_peep (operands[1], operands[3])
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&& registers_ok_for_quad_peep (operands[1], operands[3])
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&& mems_ok_for_quad_peep (operands[0], operands[2])"
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&& mems_ok_for_quad_peep (operands[0], operands[2])"
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[(set (match_dup 0)
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[(set (match_dup 0)
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@ -11935,7 +11899,7 @@
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[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
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[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
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|
(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
|
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(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
|
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(match_operand:SF 2 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:SF 2 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"fcmpu %0,%1,%2"
|
|
|
|
"fcmpu %0,%1,%2"
|
|
|
|
[(set_attr "type" "fpcompare")])
|
|
|
|
[(set_attr "type" "fpcompare")])
|
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|
|
|
|
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|
|
|
|
@ -11943,7 +11907,7 @@
|
|
|
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
|
|
|
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
|
|
|
|
(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
|
|
|
|
(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:DF 2 "gpc_reg_operand" "f")))]
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
|
|
|
|
"TARGET_HARD_FLOAT && TARGET_FPRS"
|
|
|
|
"fcmpu %0,%1,%2"
|
|
|
|
"fcmpu %0,%1,%2"
|
|
|
|
[(set_attr "type" "fpcompare")])
|
|
|
|
[(set_attr "type" "fpcompare")])
|
|
|
|
|
|
|
|
|
|
|
@ -11953,7 +11917,7 @@
|
|
|
|
(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
|
|
|
|
(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
|
|
|
|
(match_operand:TF 2 "gpc_reg_operand" "f")))]
|
|
|
|
(match_operand:TF 2 "gpc_reg_operand" "f")))]
|
|
|
|
"!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
|
|
|
|
"!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
|
|
|
|
"fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
|
|
|
|
"fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
|
|
|
|
[(set_attr "type" "fpcompare")
|
|
|
|
[(set_attr "type" "fpcompare")
|
|
|
|
(set_attr "length" "12")])
|
|
|
|
(set_attr "length" "12")])
|
|
|
@ -11971,7 +11935,7 @@
|
|
|
|
(clobber (match_scratch:DF 9 "=f"))
|
|
|
|
(clobber (match_scratch:DF 9 "=f"))
|
|
|
|
(clobber (match_scratch:DF 10 "=f"))]
|
|
|
|
(clobber (match_scratch:DF 10 "=f"))]
|
|
|
|
"!TARGET_IEEEQUAD && TARGET_XL_COMPAT
|
|
|
|
"!TARGET_IEEEQUAD && TARGET_XL_COMPAT
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
|
|
|
|
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
|
|
|
|
"#"
|
|
|
|
"#"
|
|
|
|
"&& reload_completed"
|
|
|
|
"&& reload_completed"
|
|
|
|
[(set (match_dup 3) (match_dup 13))
|
|
|
|
[(set (match_dup 3) (match_dup 13))
|
|
|
|