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Revert rs6000 change. 

From-SVN: r140646
This commit is contained in:
David Edelsohn 2008-09-24 21:58:36 +00:00 committed by David Edelsohn
parent 1547a82040
commit cf8e1455a4
9 changed files with 167 additions and 318 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2008-09-24 David Edelsohn <edelsohn@gnu.org>
Revert:
2008-09-24 Michael J. Eager <eager@eagercon.com>
2008-09-24 Aldy Hernandez <aldyh@redhat.com> 2008-09-24 Aldy Hernandez <aldyh@redhat.com>
* c-common.c (fname_decl): New location argument. * c-common.c (fname_decl): New location argument.

5
gcc/config.gcc
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@ -1791,11 +1791,6 @@ powerpc-*-eabialtivec*)
extra_options="${extra_options} rs6000/sysv4.opt" extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcendian rs6000/t-ppccomm" tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcendian rs6000/t-ppccomm"
;; ;;
powerpc-xilinx-eabi*)
tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
;;
powerpc-*-eabi*) powerpc-*-eabi*)
tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h" tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h"
extra_options="${extra_options} rs6000/sysv4.opt" extra_options="${extra_options} rs6000/sysv4.opt"

3
gcc/config/rs6000/predicates.md
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@ -192,8 +192,7 @@
return 0; return 0;
/* Consider all constants with -msoft-float to be easy. */ /* Consider all constants with -msoft-float to be easy. */
if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
|| (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
&& mode != DImode) && mode != DImode)
return 1; return 1;

3
gcc/config/rs6000/rs6000-c.c
View File

@ -297,8 +297,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
builtin_define ("__PAIRED__"); builtin_define ("__PAIRED__");
if (TARGET_SOFT_FLOAT) if (TARGET_SOFT_FLOAT)
builtin_define ("_SOFT_FLOAT"); builtin_define ("_SOFT_FLOAT");
if ((!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE))) if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
||(TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_DOUBLE_FLOAT))
builtin_define ("_SOFT_DOUBLE"); builtin_define ("_SOFT_DOUBLE");
/* Used by lwarx/stwcx. errata work-around. */ /* Used by lwarx/stwcx. errata work-around. */
if (rs6000_cpu == PROCESSOR_PPC405) if (rs6000_cpu == PROCESSOR_PPC405)

157
gcc/config/rs6000/rs6000.c
View File

@ -1556,6 +1556,8 @@ rs6000_override_options (const char *default_cpu)
| MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP) | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
}; };
rs6000_init_hard_regno_mode_ok ();
set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT; set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
#ifdef OS_MISSING_POWERPC64 #ifdef OS_MISSING_POWERPC64
if (OS_MISSING_POWERPC64) if (OS_MISSING_POWERPC64)
@ -1966,25 +1968,6 @@ rs6000_override_options (const char *default_cpu)
can be optimized to ap = __builtin_next_arg (0). */ can be optimized to ap = __builtin_next_arg (0). */
if (DEFAULT_ABI != ABI_V4) if (DEFAULT_ABI != ABI_V4)
targetm.expand_builtin_va_start = NULL; targetm.expand_builtin_va_start = NULL;
/* Set up single/double float flags.
If TARGET_HARD_FLOAT is set, but neither single or double is set,
then set both flags. */
if (TARGET_HARD_FLOAT && TARGET_FPRS
&& rs6000_single_float == 0 && rs6000_double_float == 0)
rs6000_single_float = rs6000_double_float = 1;
/* Reset single and double FP flags if target is E500. */
if (TARGET_E500)
{
rs6000_single_float = rs6000_double_float = 0;
if (TARGET_E500_SINGLE)
rs6000_single_float = 1;
if (TARGET_E500_DOUBLE)
rs6000_single_float = rs6000_double_float = 1;
}
rs6000_init_hard_regno_mode_ok ();
} }
/* Implement targetm.vectorize.builtin_mask_for_load. */ /* Implement targetm.vectorize.builtin_mask_for_load. */
@ -2494,37 +2477,6 @@ rs6000_handle_option (size_t code, const char *arg, int value)
return false; return false;
} }
break; break;
case OPT_msingle_float:
if (!TARGET_SINGLE_FPU)
warning (0, "-msingle-float option equivalent to -mhard-float");
/* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */
rs6000_double_float = 0;
target_flags &= ~MASK_SOFT_FLOAT;
target_flags_explicit |= MASK_SOFT_FLOAT;
break;
case OPT_mdouble_float:
/* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */
rs6000_single_float = 1;
target_flags &= ~MASK_SOFT_FLOAT;
target_flags_explicit |= MASK_SOFT_FLOAT;
break;
case OPT_msimple_fpu:
if (!TARGET_SINGLE_FPU)
warning (0, "-msimple-fpu option ignored");
break;
case OPT_mhard_float:
/* -mhard_float implies -msingle-float and -mdouble-float. */
rs6000_single_float = rs6000_double_float = 1;
break;
case OPT_msoft_float:
/* -msoft_float implies -mnosingle-float and -mnodouble-float. */
rs6000_single_float = rs6000_double_float = 0;
break;
} }
return true; return true;
} }
@ -2594,9 +2546,7 @@ rs6000_file_start (void)
if (TARGET_32BIT && DEFAULT_ABI == ABI_V4) if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
{ {
fprintf (file, "\t.gnu_attribute 4, %d\n", fprintf (file, "\t.gnu_attribute 4, %d\n",
((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
: (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3
: 2));
fprintf (file, "\t.gnu_attribute 8, %d\n", fprintf (file, "\t.gnu_attribute 8, %d\n",
(TARGET_ALTIVEC_ABI ? 2 (TARGET_ALTIVEC_ABI ? 2
: TARGET_SPE_ABI ? 3 : TARGET_SPE_ABI ? 3
@ -3741,7 +3691,7 @@ legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
return false; return false;
if (GET_MODE_BITSIZE (mode) > 64 if (GET_MODE_BITSIZE (mode) > 64
|| (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
&& !(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !(TARGET_HARD_FLOAT && TARGET_FPRS
&& (mode == DFmode || mode == DDmode)))) && (mode == DFmode || mode == DDmode))))
return false; return false;
@ -3808,7 +3758,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& GET_CODE (XEXP (x, 0)) == REG && GET_CODE (XEXP (x, 0)) == REG
&& GET_CODE (XEXP (x, 1)) != CONST_INT && GET_CODE (XEXP (x, 1)) != CONST_INT
&& GET_MODE_NUNITS (mode) == 1 && GET_MODE_NUNITS (mode) == 1
&& ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) && ((TARGET_HARD_FLOAT && TARGET_FPRS)
|| TARGET_POWERPC64 || TARGET_POWERPC64
|| ((mode != DImode && mode != DFmode && mode != DDmode) || ((mode != DImode && mode != DFmode && mode != DDmode)
|| (TARGET_E500_DOUBLE && mode != DDmode))) || (TARGET_E500_DOUBLE && mode != DDmode)))
@ -3877,7 +3827,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& CONSTANT_P (x) && CONSTANT_P (x)
&& GET_MODE_NUNITS (mode) == 1 && GET_MODE_NUNITS (mode) == 1
&& (GET_MODE_BITSIZE (mode) <= 32 && (GET_MODE_BITSIZE (mode) <= 32
|| ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) || ((TARGET_HARD_FLOAT && TARGET_FPRS)
&& (mode == DFmode || mode == DDmode)))) && (mode == DFmode || mode == DDmode))))
{ {
rtx reg = gen_reg_rtx (Pmode); rtx reg = gen_reg_rtx (Pmode);
@ -3892,7 +3842,7 @@ rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_INT
&& GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_DOUBLE
&& CONSTANT_P (x) && CONSTANT_P (x)
&& ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) && ((TARGET_HARD_FLOAT && TARGET_FPRS)
|| (mode != DFmode && mode != DDmode)) || (mode != DFmode && mode != DDmode))
&& mode != DImode && mode != DImode
&& mode != TImode) && mode != TImode)
@ -4309,7 +4259,7 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
&& mode != TDmode && mode != TDmode
&& (mode != DImode || TARGET_POWERPC64) && (mode != DImode || TARGET_POWERPC64)
&& ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
|| (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT))) || (TARGET_FPRS && TARGET_HARD_FLOAT)))
{ {
#if TARGET_MACHO #if TARGET_MACHO
if (flag_pic) if (flag_pic)
@ -4434,7 +4384,7 @@ rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
&& mode != TImode && mode != TImode
&& mode != TFmode && mode != TFmode
&& mode != TDmode && mode != TDmode
&& ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) && ((TARGET_HARD_FLOAT && TARGET_FPRS)
|| TARGET_POWERPC64 || TARGET_POWERPC64
|| ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE)) || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
&& (TARGET_POWERPC64 || mode != DImode) && (TARGET_POWERPC64 || mode != DImode)
@ -4889,7 +4839,7 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
operands[1] = force_reg (mode, operands[1]); operands[1] = force_reg (mode, operands[1]);
if (mode == SFmode && ! TARGET_POWERPC if (mode == SFmode && ! TARGET_POWERPC
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS
&& GET_CODE (operands[0]) == MEM) && GET_CODE (operands[0]) == MEM)
{ {
int regnum; int regnum;
@ -5250,9 +5200,7 @@ rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
(SCALAR_FLOAT_MODE_P (MODE) \ (SCALAR_FLOAT_MODE_P (MODE) \
&& (CUM)->fregno <= FP_ARG_MAX_REG \ && (CUM)->fregno <= FP_ARG_MAX_REG \
&& TARGET_HARD_FLOAT && TARGET_FPRS \ && TARGET_HARD_FLOAT && TARGET_FPRS)
&& (TARGET_DOUBLE_FLOAT_MODE (MODE) \
|| TARGET_SINGLE_FLOAT_MODE (MODE)))
/* Nonzero if we can use an AltiVec register to pass this arg. */ /* Nonzero if we can use an AltiVec register to pass this arg. */
#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \ #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
@ -5729,10 +5677,9 @@ function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
else if (DEFAULT_ABI == ABI_V4) else if (DEFAULT_ABI == ABI_V4)
{ {
if (TARGET_HARD_FLOAT && TARGET_FPRS if (TARGET_HARD_FLOAT && TARGET_FPRS
&& (TARGET_SINGLE_FLOAT_MODE (mode) && (mode == SFmode || mode == DFmode
|| (TARGET_DOUBLE_FLOAT || mode == SDmode || mode == DDmode || mode == TDmode
&& (mode == DFmode || mode == DDmode || mode == TDmode)) || (mode == TFmode && !TARGET_IEEEQUAD)))
|| (mode == TFmode && !TARGET_IEEEQUAD)))
{ {
/* _Decimal128 must use an even/odd register pair. This assumes /* _Decimal128 must use an even/odd register pair. This assumes
that the register number is odd when fregno is odd. */ that the register number is odd when fregno is odd. */
@ -5798,8 +5745,7 @@ function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
cum->words = align_words + n_words; cum->words = align_words + n_words;
if (SCALAR_FLOAT_MODE_P (mode) if (SCALAR_FLOAT_MODE_P (mode)
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_HARD_FLOAT && TARGET_FPRS)
&& (TARGET_DOUBLE_FLOAT_MODE (mode) || TARGET_SINGLE_FLOAT_MODE (mode)))
{ {
/* _Decimal128 must be passed in an even/odd float register pair. /* _Decimal128 must be passed in an even/odd float register pair.
This assumes that the register number is odd when fregno is This assumes that the register number is odd when fregno is
@ -6293,10 +6239,9 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
else if (abi == ABI_V4) else if (abi == ABI_V4)
{ {
if (TARGET_HARD_FLOAT && TARGET_FPRS if (TARGET_HARD_FLOAT && TARGET_FPRS
&& (TARGET_SINGLE_FLOAT_MODE(mode) && (mode == SFmode || mode == DFmode
|| (TARGET_DOUBLE_FLOAT && (mode == SFmode || mode == DFmode)) || (mode == TFmode && !TARGET_IEEEQUAD)
&& ((mode == TFmode && !TARGET_IEEEQUAD) || mode == SDmode || mode == DDmode || mode == TDmode))
|| mode == SDmode || mode == DDmode || mode == TDmode)))
{ {
/* _Decimal128 must use an even/odd register pair. This assumes /* _Decimal128 must use an even/odd register pair. This assumes
that the register number is odd when fregno is odd. */ that the register number is odd when fregno is odd. */
@ -6756,17 +6701,11 @@ setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size; fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
fregno++, off += UNITS_PER_FP_WORD, nregs++) fregno++, off += UNITS_PER_FP_WORD, nregs++)
{ {
mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
? DFmode : SFmode, MEM_NOTRAP_P (mem) = 1;
plus_constant (save_area, off)); set_mem_alias_set (mem, set);
MEM_NOTRAP_P (mem) = 1; set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
set_mem_alias_set (mem, set); emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
set_mem_align (mem, GET_MODE_ALIGNMENT (
(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
? DFmode : SFmode));
emit_move_insn (mem, gen_rtx_REG (
(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
? DFmode : SFmode, fregno));
} }
emit_label (lab); emit_label (lab);
@ -6981,19 +6920,18 @@ rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
align = 1; align = 1;
if (TARGET_HARD_FLOAT && TARGET_FPRS if (TARGET_HARD_FLOAT && TARGET_FPRS
&& (TARGET_SINGLE_FLOAT_MODE (TYPE_MODE (type)) && (TYPE_MODE (type) == SFmode
|| (TARGET_DOUBLE_FLOAT || TYPE_MODE (type) == DFmode
&& (TYPE_MODE (type) == DFmode || TYPE_MODE (type) == TFmode
|| TYPE_MODE (type) == TFmode || TYPE_MODE (type) == SDmode
|| TYPE_MODE (type) == SDmode || TYPE_MODE (type) == DDmode
|| TYPE_MODE (type) == DDmode || TYPE_MODE (type) == TDmode))
|| TYPE_MODE (type) == TDmode))))
{ {
/* FP args go in FP registers, if present. */ /* FP args go in FP registers, if present. */
reg = fpr; reg = fpr;
n_reg = (size + 7) / 8; n_reg = (size + 7) / 8;
sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4; sav_ofs = 8*4;
sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4); sav_scale = 8;
if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode) if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
align = 8; align = 8;
} }
@ -14189,8 +14127,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
mode = GET_MODE (dst); mode = GET_MODE (dst);
nregs = hard_regno_nregs[reg][mode]; nregs = hard_regno_nregs[reg][mode];
if (FP_REGNO_P (reg)) if (FP_REGNO_P (reg))
reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
else if (ALTIVEC_REGNO_P (reg)) else if (ALTIVEC_REGNO_P (reg))
reg_mode = V16QImode; reg_mode = V16QImode;
else if (TARGET_E500_DOUBLE && mode == TFmode) else if (TARGET_E500_DOUBLE && mode == TFmode)
@ -16142,14 +16079,11 @@ rs6000_emit_prologue (void)
properly. */ properly. */
for (i = 0; i < 64 - info->first_fp_reg_save; i++) for (i = 0; i < 64 - info->first_fp_reg_save; i++)
{ {
rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
? DFmode : SFmode),
info->first_fp_reg_save + i);
rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
GEN_INT (info->fp_save_offset GEN_INT (info->fp_save_offset
+ sp_offset + 8 * i)); + sp_offset + 8 * i));
rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) rtx mem = gen_frame_mem (DFmode, addr);
? DFmode : SFmode), addr);
RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg); RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
} }
@ -16256,9 +16190,7 @@ rs6000_emit_prologue (void)
for (i = 0; i < 64 - info->first_fp_reg_save; i++) for (i = 0; i < 64 - info->first_fp_reg_save; i++)
if ((df_regs_ever_live_p (info->first_fp_reg_save+i) if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
&& ! call_used_regs[info->first_fp_reg_save+i])) && ! call_used_regs[info->first_fp_reg_save+i]))
emit_frame_save (frame_reg_rtx, frame_ptr_rtx, emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
(TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
? DFmode : SFmode,
info->first_fp_reg_save + i, info->first_fp_reg_save + i,
info->fp_save_offset + sp_offset + 8 * i, info->fp_save_offset + sp_offset + 8 * i,
info->total_size); info->total_size);
@ -16903,14 +16835,11 @@ rs6000_emit_epilogue (int sibcall)
} }
for (i = 0; info->first_fp_reg_save + i <= 63; i++) for (i = 0; info->first_fp_reg_save + i <= 63; i++)
{ {
rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
? DFmode : SFmode),
info->first_fp_reg_save + i);
rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
GEN_INT (info->fp_save_offset GEN_INT (info->fp_save_offset
+ 8 * i)); + 8 * i));
rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) rtx mem = gen_frame_mem (DFmode, addr);
? DFmode : SFmode), addr);
RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem); RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
} }
@ -17315,12 +17244,9 @@ rs6000_emit_epilogue (int sibcall)
GEN_INT (info->fp_save_offset GEN_INT (info->fp_save_offset
+ sp_offset + sp_offset
+ 8 * i)); + 8 * i));
mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) mem = gen_frame_mem (DFmode, addr);
? DFmode : SFmode), addr);
emit_move_insn (gen_rtx_REG (((TARGET_HARD_FLOAT emit_move_insn (gen_rtx_REG (DFmode,
&& TARGET_DOUBLE_FLOAT)
? DFmode : SFmode),
info->first_fp_reg_save + i), info->first_fp_reg_save + i),
mem); mem);
} }
@ -22460,10 +22386,7 @@ rs6000_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS) if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
/* _Decimal128 must use an even/odd register pair. */ /* _Decimal128 must use an even/odd register pair. */
regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN; regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_FPRS else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
&& (TARGET_HARD_FLOAT
&& (TARGET_SINGLE_FLOAT_MODE (mode)
|| TARGET_DOUBLE_FLOAT)))
regno = FP_ARG_RETURN; regno = FP_ARG_RETURN;
else if (TREE_CODE (valtype) == COMPLEX_TYPE else if (TREE_CODE (valtype) == COMPLEX_TYPE
&& targetm.calls.split_complex_arg) && targetm.calls.split_complex_arg)

11
gcc/config/rs6000/rs6000.h
View File

@ -298,17 +298,6 @@ enum processor_type
PROCESSOR_CELL PROCESSOR_CELL
}; };
/* FPU operations supported.
Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
also test TARGET_HARD_FLOAT. */
#define TARGET_SINGLE_FLOAT 1
#define TARGET_DOUBLE_FLOAT 1
#define TARGET_SINGLE_FPU 0
#define TARGET_SIMPLE_FPU 0
#define TARGET_SINGLE_FLOAT_MODE(MODE) (TARGET_SINGLE_FLOAT && (MODE) == SFmode)
#define TARGET_DOUBLE_FLOAT_MODE(MODE) (TARGET_DOUBLE_FLOAT && (MODE) == DFmode)
extern enum processor_type rs6000_cpu; extern enum processor_type rs6000_cpu;
/* Recast the processor type to the cpu attribute. */ /* Recast the processor type to the cpu attribute. */

268
gcc/config/rs6000/rs6000.md
View File

@ -202,11 +202,8 @@
(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
; Any hardware-supported floating-point mode ; Any hardware-supported floating-point mode
(define_mode_iterator FP [ (define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
(SF "TARGET_HARD_FLOAT (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
&& ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
(DF "TARGET_HARD_FLOAT
&& ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
(TF "!TARGET_IEEEQUAD (TF "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_HARD_FLOAT
&& (TARGET_FPRS || TARGET_E500_DOUBLE) && (TARGET_FPRS || TARGET_E500_DOUBLE)
@ -5062,13 +5059,13 @@
(define_expand "extendsfdf2" (define_expand "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "") [(set (match_operand:DF 0 "gpc_reg_operand" "")
(float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))] (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn_and_split "*extendsfdf2_fpr" (define_insn_and_split "*extendsfdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
(float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))] (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"@ "@
# #
fmr %0,%1 fmr %0,%1
@ -5084,53 +5081,53 @@
(define_expand "truncdfsf2" (define_expand "truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "*truncdfsf2_fpr" (define_insn "*truncdfsf2_fpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"frsp %0,%1" "frsp %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "aux_truncdfsf2" (define_insn "aux_truncdfsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
"frsp %0,%1" "frsp %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "negsf2" (define_expand "negsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT"
"") "")
(define_insn "*negsf2" (define_insn "*negsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1" "fneg %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "abssf2" (define_expand "abssf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT"
"") "")
(define_insn "*abssf2" (define_insn "*abssf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1" "fabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1" "fnabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5138,14 +5135,14 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")))] (match_operand:SF 2 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT"
"") "")
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
"fadds %0,%1,%2" "fadds %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5153,7 +5150,7 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
"{fa|fadd} %0,%1,%2" "{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5161,14 +5158,14 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")))] (match_operand:SF 2 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT"
"") "")
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
"fsubs %0,%1,%2" "fsubs %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5176,7 +5173,7 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
"{fs|fsub} %0,%1,%2" "{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5184,14 +5181,14 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")))] (match_operand:SF 2 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT"
"") "")
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
"fmuls %0,%1,%2" "fmuls %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5199,7 +5196,7 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
"{fm|fmul} %0,%1,%2" "{fm|fmul} %0,%1,%2"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5207,15 +5204,14 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "") (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")))] (match_operand:SF 2 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" "TARGET_HARD_FLOAT"
"") "")
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f") (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
"fdivs %0,%1,%2" "fdivs %0,%1,%2"
[(set_attr "type" "sdiv")]) [(set_attr "type" "sdiv")])
@ -5223,8 +5219,7 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(div:SF (match_operand:SF 1 "gpc_reg_operand" "f") (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
"{fd|fdiv} %0,%1,%2" "{fd|fdiv} %0,%1,%2"
[(set_attr "type" "ddiv")]) [(set_attr "type" "ddiv")])
@ -5252,8 +5247,7 @@
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
"fmadds %0,%1,%2,%3" "fmadds %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5262,8 +5256,7 @@
(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
"{fma|fmadd} %0,%1,%2,%3" "{fma|fmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5272,8 +5265,7 @@
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
"fmsubs %0,%1,%2,%3" "fmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5282,8 +5274,7 @@
(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
"{fms|fmsub} %0,%1,%2,%3" "{fms|fmsub} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5293,7 +5284,7 @@
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)" && HONOR_SIGNED_ZEROS (SFmode)"
"fnmadds %0,%1,%2,%3" "fnmadds %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5302,7 +5293,7 @@
(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& ! HONOR_SIGNED_ZEROS (SFmode)" && ! HONOR_SIGNED_ZEROS (SFmode)"
"fnmadds %0,%1,%2,%3" "fnmadds %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5312,8 +5303,7 @@
(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
"{fnma|fnmadd} %0,%1,%2,%3" "{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5323,7 +5313,7 @@
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)" && ! HONOR_SIGNED_ZEROS (SFmode)"
"{fnma|fnmadd} %0,%1,%2,%3" "{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5333,7 +5323,7 @@
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)" && HONOR_SIGNED_ZEROS (SFmode)"
"fnmsubs %0,%1,%2,%3" "fnmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5343,7 +5333,7 @@
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))))] (match_operand:SF 2 "gpc_reg_operand" "f"))))]
"TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)" && ! HONOR_SIGNED_ZEROS (SFmode)"
"fnmsubs %0,%1,%2,%3" "fnmsubs %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5352,8 +5342,7 @@
(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 2 "gpc_reg_operand" "f"))
(match_operand:SF 3 "gpc_reg_operand" "f"))))] (match_operand:SF 3 "gpc_reg_operand" "f"))))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
&& TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
"{fnms|fnmsub} %0,%1,%2,%3" "{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5363,31 +5352,27 @@
(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
(match_operand:SF 2 "gpc_reg_operand" "f"))))] (match_operand:SF 2 "gpc_reg_operand" "f"))))]
"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)" && ! HONOR_SIGNED_ZEROS (SFmode)"
"{fnms|fnmsub} %0,%1,%2,%3" "{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
(define_expand "sqrtsf2" (define_expand "sqrtsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
"(TARGET_PPC_GPOPT || TARGET_POWER2) "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
&& !TARGET_SIMPLE_FPU"
"") "")
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
"TARGET_PPC_GPOPT && TARGET_HARD_FLOAT "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
"fsqrts %0,%1" "fsqrts %0,%1"
[(set_attr "type" "ssqrt")]) [(set_attr "type" "ssqrt")])
(define_insn "" (define_insn ""
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
"TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
"fsqrt %0,%1" "fsqrt %0,%1"
[(set_attr "type" "dsqrt")]) [(set_attr "type" "dsqrt")])
@ -5420,7 +5405,7 @@
(match_dup 5)) (match_dup 5))
(match_dup 3) (match_dup 3)
(match_dup 4)))] (match_dup 4)))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
&& !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)" && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
{ {
operands[3] = gen_reg_rtx (SFmode); operands[3] = gen_reg_rtx (SFmode);
@ -5438,7 +5423,7 @@
(match_dup 5)) (match_dup 5))
(match_dup 3) (match_dup 3)
(match_dup 4)))] (match_dup 4)))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
&& !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)" && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
{ {
operands[3] = gen_reg_rtx (DFmode); operands[3] = gen_reg_rtx (DFmode);
@ -5456,8 +5441,7 @@
(match_operand:SF 2 "gpc_reg_operand" "")) (match_operand:SF 2 "gpc_reg_operand" ""))
(match_dup 1) (match_dup 1)
(match_dup 2)))] (match_dup 2)))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
&& TARGET_SINGLE_FLOAT && !flag_trapping_math"
"{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
(define_expand "sminsf3" (define_expand "sminsf3"
@ -5466,8 +5450,7 @@
(match_operand:SF 2 "gpc_reg_operand" "")) (match_operand:SF 2 "gpc_reg_operand" ""))
(match_dup 2) (match_dup 2)
(match_dup 1)))] (match_dup 1)))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
&& TARGET_SINGLE_FLOAT && !flag_trapping_math"
"{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
(define_split (define_split
@ -5475,8 +5458,7 @@
(match_operator:SF 3 "min_max_operator" (match_operator:SF 3 "min_max_operator"
[(match_operand:SF 1 "gpc_reg_operand" "") [(match_operand:SF 1 "gpc_reg_operand" "")
(match_operand:SF 2 "gpc_reg_operand" "")]))] (match_operand:SF 2 "gpc_reg_operand" "")]))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
&& TARGET_SINGLE_FLOAT && !flag_trapping_math"
[(const_int 0)] [(const_int 0)]
" "
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
@ -5537,7 +5519,7 @@
(if_then_else:SF (match_operand 1 "comparison_operator" "") (if_then_else:SF (match_operand 1 "comparison_operator" "")
(match_operand:SF 2 "gpc_reg_operand" "") (match_operand:SF 2 "gpc_reg_operand" "")
(match_operand:SF 3 "gpc_reg_operand" "")))] (match_operand:SF 3 "gpc_reg_operand" "")))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
" "
{ {
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
@ -5552,7 +5534,7 @@
(match_operand:SF 4 "zero_fp_constant" "F")) (match_operand:SF 4 "zero_fp_constant" "F"))
(match_operand:SF 2 "gpc_reg_operand" "f") (match_operand:SF 2 "gpc_reg_operand" "f")
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
"fsel %0,%1,%2,%3" "fsel %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5562,40 +5544,40 @@
(match_operand:DF 4 "zero_fp_constant" "F")) (match_operand:DF 4 "zero_fp_constant" "F"))
(match_operand:SF 2 "gpc_reg_operand" "f") (match_operand:SF 2 "gpc_reg_operand" "f")
(match_operand:SF 3 "gpc_reg_operand" "f")))] (match_operand:SF 3 "gpc_reg_operand" "f")))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
"fsel %0,%1,%2,%3" "fsel %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "negdf2" (define_expand "negdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "") [(set (match_operand:DF 0 "gpc_reg_operand" "")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))] (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "*negdf2_fpr" (define_insn "*negdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fneg %0,%1" "fneg %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "absdf2" (define_expand "absdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "") [(set (match_operand:DF 0 "gpc_reg_operand" "")
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "*absdf2_fpr" (define_insn "*absdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fabs %0,%1" "fabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "*nabsdf2_fpr" (define_insn "*nabsdf2_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fnabs %0,%1" "fnabs %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5603,14 +5585,14 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "") [(set (match_operand:DF 0 "gpc_reg_operand" "")
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "") (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "gpc_reg_operand" "")))] (match_operand:DF 2 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "*adddf3_fpr" (define_insn "*adddf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"{fa|fadd} %0,%1,%2" "{fa|fadd} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5618,14 +5600,14 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "") [(set (match_operand:DF 0 "gpc_reg_operand" "")
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "") (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "gpc_reg_operand" "")))] (match_operand:DF 2 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "*subdf3_fpr" (define_insn "*subdf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"{fs|fsub} %0,%1,%2" "{fs|fsub} %0,%1,%2"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5633,14 +5615,14 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "") [(set (match_operand:DF 0 "gpc_reg_operand" "")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "gpc_reg_operand" "")))] (match_operand:DF 2 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "*muldf3_fpr" (define_insn "*muldf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"{fm|fmul} %0,%1,%2" "{fm|fmul} %0,%1,%2"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5648,14 +5630,14 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "") [(set (match_operand:DF 0 "gpc_reg_operand" "")
(div:DF (match_operand:DF 1 "gpc_reg_operand" "") (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "gpc_reg_operand" "")))] (match_operand:DF 2 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE) && !TARGET_SIMPLE_FPU" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"") "")
(define_insn "*divdf3_fpr" (define_insn "*divdf3_fpr"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(div:DF (match_operand:DF 1 "gpc_reg_operand" "f") (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU" "TARGET_HARD_FLOAT && TARGET_FPRS"
"{fd|fdiv} %0,%1,%2" "{fd|fdiv} %0,%1,%2"
[(set_attr "type" "ddiv")]) [(set_attr "type" "ddiv")])
@ -5683,7 +5665,7 @@
(plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "f"))
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
"{fma|fmadd} %0,%1,%2,%3" "{fma|fmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5692,7 +5674,7 @@
(minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "f"))
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
"{fms|fmsub} %0,%1,%2,%3" "{fms|fmsub} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5701,7 +5683,7 @@
(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "f"))
(match_operand:DF 3 "gpc_reg_operand" "f"))))] (match_operand:DF 3 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& HONOR_SIGNED_ZEROS (DFmode)" && HONOR_SIGNED_ZEROS (DFmode)"
"{fnma|fnmadd} %0,%1,%2,%3" "{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5711,7 +5693,7 @@
(minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "f"))
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& ! HONOR_SIGNED_ZEROS (DFmode)" && ! HONOR_SIGNED_ZEROS (DFmode)"
"{fnma|fnmadd} %0,%1,%2,%3" "{fnma|fnmadd} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5721,7 +5703,7 @@
(neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 2 "gpc_reg_operand" "f"))
(match_operand:DF 3 "gpc_reg_operand" "f"))))] (match_operand:DF 3 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& HONOR_SIGNED_ZEROS (DFmode)" && HONOR_SIGNED_ZEROS (DFmode)"
"{fnms|fnmsub} %0,%1,%2,%3" "{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5731,7 +5713,7 @@
(minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
(match_operand:DF 2 "gpc_reg_operand" "f"))))] (match_operand:DF 2 "gpc_reg_operand" "f"))))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
&& ! HONOR_SIGNED_ZEROS (DFmode)" && ! HONOR_SIGNED_ZEROS (DFmode)"
"{fnms|fnmsub} %0,%1,%2,%3" "{fnms|fnmsub} %0,%1,%2,%3"
[(set_attr "type" "dmul")]) [(set_attr "type" "dmul")])
@ -5739,8 +5721,7 @@
(define_insn "sqrtdf2" (define_insn "sqrtdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_DOUBLE_FLOAT"
"fsqrt %0,%1" "fsqrt %0,%1"
[(set_attr "type" "dsqrt")]) [(set_attr "type" "dsqrt")])
@ -5753,8 +5734,7 @@
(match_operand:DF 2 "gpc_reg_operand" "")) (match_operand:DF 2 "gpc_reg_operand" ""))
(match_dup 1) (match_dup 1)
(match_dup 2)))] (match_dup 2)))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
&& !flag_trapping_math"
"{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
(define_expand "smindf3" (define_expand "smindf3"
@ -5763,8 +5743,7 @@
(match_operand:DF 2 "gpc_reg_operand" "")) (match_operand:DF 2 "gpc_reg_operand" ""))
(match_dup 2) (match_dup 2)
(match_dup 1)))] (match_dup 1)))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
&& !flag_trapping_math"
"{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
(define_split (define_split
@ -5772,8 +5751,7 @@
(match_operator:DF 3 "min_max_operator" (match_operator:DF 3 "min_max_operator"
[(match_operand:DF 1 "gpc_reg_operand" "") [(match_operand:DF 1 "gpc_reg_operand" "")
(match_operand:DF 2 "gpc_reg_operand" "")]))] (match_operand:DF 2 "gpc_reg_operand" "")]))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
&& !flag_trapping_math"
[(const_int 0)] [(const_int 0)]
" "
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
@ -5786,7 +5764,7 @@
(if_then_else:DF (match_operand 1 "comparison_operator" "") (if_then_else:DF (match_operand 1 "comparison_operator" "")
(match_operand:DF 2 "gpc_reg_operand" "") (match_operand:DF 2 "gpc_reg_operand" "")
(match_operand:DF 3 "gpc_reg_operand" "")))] (match_operand:DF 3 "gpc_reg_operand" "")))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
" "
{ {
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
@ -5801,7 +5779,7 @@
(match_operand:DF 4 "zero_fp_constant" "F")) (match_operand:DF 4 "zero_fp_constant" "F"))
(match_operand:DF 2 "gpc_reg_operand" "f") (match_operand:DF 2 "gpc_reg_operand" "f")
(match_operand:DF 3 "gpc_reg_operand" "f")))] (match_operand:DF 3 "gpc_reg_operand" "f")))]
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
"fsel %0,%1,%2,%3" "fsel %0,%1,%2,%3"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -5820,13 +5798,13 @@
(define_expand "fixuns_truncsfsi2" (define_expand "fixuns_truncsfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "") [(set (match_operand:SI 0 "gpc_reg_operand" "")
(unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT && !TARGET_FPRS"
"") "")
(define_expand "fix_truncsfsi2" (define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "") [(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT && !TARGET_FPRS"
"") "")
; For each of these conversions, there is a define_expand, a define_insn ; For each of these conversions, there is a define_expand, a define_insn
@ -5842,8 +5820,7 @@
(clobber (match_dup 4)) (clobber (match_dup 4))
(clobber (match_dup 5)) (clobber (match_dup 5))
(clobber (match_dup 6))])] (clobber (match_dup 6))])]
"TARGET_HARD_FLOAT "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
&& ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
" "
{ {
if (TARGET_E500_DOUBLE) if (TARGET_E500_DOUBLE)
@ -5873,7 +5850,7 @@
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o")) (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
(clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"#" "#"
"&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))" "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
[(pc)] [(pc)]
@ -5902,7 +5879,7 @@
(define_expand "floatunssisf2" (define_expand "floatunssisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT && !TARGET_FPRS"
"") "")
(define_expand "floatunssidf2" (define_expand "floatunssidf2"
@ -5912,7 +5889,7 @@
(use (match_dup 3)) (use (match_dup 3))
(clobber (match_dup 4)) (clobber (match_dup 4))
(clobber (match_dup 5))])] (clobber (match_dup 5))])]
"TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
" "
{ {
if (TARGET_E500_DOUBLE) if (TARGET_E500_DOUBLE)
@ -5940,7 +5917,7 @@
(use (match_operand:DF 3 "gpc_reg_operand" "f")) (use (match_operand:DF 3 "gpc_reg_operand" "f"))
(clobber (match_operand:DF 4 "offsettable_mem_operand" "=o")) (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
(clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"#" "#"
"&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))" "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
[(pc)] [(pc)]
@ -5970,7 +5947,7 @@
(clobber (match_dup 2)) (clobber (match_dup 2))
(clobber (match_dup 3))])] (clobber (match_dup 3))])]
"(TARGET_POWER2 || TARGET_POWERPC) "(TARGET_POWER2 || TARGET_POWERPC)
&& TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
" "
{ {
if (TARGET_E500_DOUBLE) if (TARGET_E500_DOUBLE)
@ -6006,8 +5983,7 @@
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))] (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_DOUBLE_FLOAT"
"#" "#"
"&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))" "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
[(pc)] [(pc)]
@ -6029,7 +6005,6 @@
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))] (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
&& TARGET_PPC_GFXOPT" && TARGET_PPC_GFXOPT"
"#" "#"
"&& 1" "&& 1"
@ -6047,8 +6022,7 @@
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
(clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))] (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_DOUBLE_FLOAT"
"#" "#"
"&& 1" "&& 1"
[(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ)) [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
@ -6065,64 +6039,63 @@
[(set (match_operand:DI 0 "gpc_reg_operand" "=f") [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
UNSPEC_FCTIWZ))] UNSPEC_FCTIWZ))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
&& TARGET_DOUBLE_FLOAT"
"{fcirz|fctiwz} %0,%1" "{fcirz|fctiwz} %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "btruncdf2" (define_insn "btruncdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))] (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
"friz %0,%1" "friz %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "btruncsf2" (define_insn "btruncsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))] (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT " "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
"friz %0,%1" "friz %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "ceildf2" (define_insn "ceildf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))] (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
"frip %0,%1" "frip %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "ceilsf2" (define_insn "ceilsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))] (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT " "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
"frip %0,%1" "frip %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "floordf2" (define_insn "floordf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))] (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
"frim %0,%1" "frim %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "floorsf2" (define_insn "floorsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))] (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT " "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
"frim %0,%1" "frim %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "rounddf2" (define_insn "rounddf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))] (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
"frin %0,%1" "frin %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "roundsf2" (define_insn "roundsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))] (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
"TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT " "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
"frin %0,%1" "frin %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -6138,27 +6111,27 @@
(define_expand "floatsisf2" (define_expand "floatsisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && (!TARGET_FPRS || TARGET_SINGLE_FPU)" "TARGET_HARD_FLOAT && !TARGET_FPRS"
"") "")
(define_insn "floatdidf2" (define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))] (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"fcfid %0,%1" "fcfid %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_insn "fix_truncdfdi2" (define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r") [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"fctidz %0,%1" "fctidz %0,%1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
(define_expand "floatdisf2" (define_expand "floatdisf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "") [(set (match_operand:SF 0 "gpc_reg_operand" "")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT " "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
" "
{ {
rtx val = operands[1]; rtx val = operands[1];
@ -6180,7 +6153,7 @@
[(set (match_operand:SF 0 "gpc_reg_operand" "=f") [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
(float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r"))) (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
(clobber (match_scratch:DF 2 "=f"))] (clobber (match_scratch:DF 2 "=f"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
@ -6214,7 +6187,7 @@
(label_ref (match_operand:DI 2 "" "")) (label_ref (match_operand:DI 2 "" ""))
(pc))) (pc)))
(set (match_dup 0) (match_dup 1))] (set (match_dup 0) (match_dup 1))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
" "
{ {
operands[3] = gen_reg_rtx (DImode); operands[3] = gen_reg_rtx (DImode);
@ -8246,7 +8219,7 @@
(match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
"(gpc_reg_operand (operands[0], SFmode) "(gpc_reg_operand (operands[0], SFmode)
|| gpc_reg_operand (operands[1], SFmode)) || gpc_reg_operand (operands[1], SFmode))
&& (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)" && (TARGET_HARD_FLOAT && TARGET_FPRS)"
"@ "@
mr %0,%1 mr %0,%1
{l%U1%X1|lwz%U1%X1} %0,%1 {l%U1%X1|lwz%U1%X1} %0,%1
@ -8384,7 +8357,7 @@
(define_insn "*movdf_hardfloat32" (define_insn "*movdf_hardfloat32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
(match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DFmode) && (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))" || gpc_reg_operand (operands[1], DFmode))"
"* "*
@ -8479,9 +8452,7 @@
(define_insn "*movdf_softfloat32" (define_insn "*movdf_softfloat32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
(match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
"! TARGET_POWERPC64 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
&& ((TARGET_FPRS && !TARGET_DOUBLE_FLOAT)
|| TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
&& (gpc_reg_operand (operands[0], DFmode) && (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))" || gpc_reg_operand (operands[1], DFmode))"
"* "*
@ -8525,7 +8496,6 @@
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f") [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))] (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
"TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], DFmode) && (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))" || gpc_reg_operand (operands[1], DFmode))"
"@ "@
@ -8552,7 +8522,6 @@
[(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r") [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
"TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], DFmode) && (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))" || gpc_reg_operand (operands[1], DFmode))"
"@ "@
@ -8645,8 +8614,7 @@
(float_extend:TF (match_operand:DF 1 "input_operand" ""))) (float_extend:TF (match_operand:DF 1 "input_operand" "")))
(use (match_dup 2))])] (use (match_dup 2))])]
"!TARGET_IEEEQUAD "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
&& TARGET_LONG_DOUBLE_128"
{ {
operands[2] = CONST0_RTX (DFmode); operands[2] = CONST0_RTX (DFmode);
/* Generate GOT reference early for SVR4 PIC. */ /* Generate GOT reference early for SVR4 PIC. */
@ -8659,8 +8627,7 @@
(float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
(use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))] (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
"!TARGET_IEEEQUAD "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
&& TARGET_LONG_DOUBLE_128"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(pc)] [(pc)]
@ -8717,8 +8684,7 @@
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
"!TARGET_IEEEQUAD && TARGET_XL_COMPAT "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
&& TARGET_LONG_DOUBLE_128"
"fadd %0,%1,%L1" "fadd %0,%1,%L1"
[(set_attr "type" "fp")]) [(set_attr "type" "fp")])
@ -8742,8 +8708,7 @@
(float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
(clobber (match_scratch:DF 2 "=f"))] (clobber (match_scratch:DF 2 "=f"))]
"!TARGET_IEEEQUAD "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
&& TARGET_LONG_DOUBLE_128"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
@ -8773,7 +8738,7 @@
(unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
UNSPEC_FIX_TRUNC_TF)) UNSPEC_FIX_TRUNC_TF))
(clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
[(set_attr "type" "fp") [(set_attr "type" "fp")
(set_attr "length" "20")]) (set_attr "length" "20")])
@ -8894,8 +8859,7 @@
(pc))) (pc)))
(set (match_dup 6) (neg:DF (match_dup 6)))] (set (match_dup 6) (neg:DF (match_dup 6)))]
"!TARGET_IEEEQUAD "!TARGET_IEEEQUAD
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
&& TARGET_LONG_DOUBLE_128"
" "
{ {
const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
@ -10046,7 +10010,7 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I")))) (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
"@ "@
lfsux %3,%0,%2 lfsux %3,%0,%2
lfsu %3,%2(%0)" lfsu %3,%2(%0)"
@ -10058,7 +10022,7 @@
(match_operand:SF 3 "gpc_reg_operand" "f,f")) (match_operand:SF 3 "gpc_reg_operand" "f,f"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
"@ "@
stfsux %3,%0,%2 stfsux %3,%0,%2
stfsu %3,%2(%0)" stfsu %3,%2(%0)"
@ -10094,7 +10058,7 @@
(match_operand:SI 2 "reg_or_short_operand" "r,I")))) (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
"@ "@
lfdux %3,%0,%2 lfdux %3,%0,%2
lfdu %3,%2(%0)" lfdu %3,%2(%0)"
@ -10106,7 +10070,7 @@
(match_operand:DF 3 "gpc_reg_operand" "f,f")) (match_operand:DF 3 "gpc_reg_operand" "f,f"))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))] (plus:SI (match_dup 1) (match_dup 2)))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE" "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
"@ "@
stfdux %3,%0,%2 stfdux %3,%0,%2
stfdu %3,%2(%0)" stfdu %3,%2(%0)"
@ -10127,7 +10091,7 @@
(set (match_operand:DF 2 "gpc_reg_operand" "") (set (match_operand:DF 2 "gpc_reg_operand" "")
(match_operand:DF 3 "memory_operand" ""))] (match_operand:DF 3 "memory_operand" ""))]
"TARGET_POWER2 "TARGET_POWER2
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS
&& registers_ok_for_quad_peep (operands[0], operands[2]) && registers_ok_for_quad_peep (operands[0], operands[2])
&& mems_ok_for_quad_peep (operands[1], operands[3])" && mems_ok_for_quad_peep (operands[1], operands[3])"
[(set (match_dup 0) [(set (match_dup 0)
@ -10149,7 +10113,7 @@
(set (match_operand:DF 2 "memory_operand" "") (set (match_operand:DF 2 "memory_operand" "")
(match_operand:DF 3 "gpc_reg_operand" ""))] (match_operand:DF 3 "gpc_reg_operand" ""))]
"TARGET_POWER2 "TARGET_POWER2
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_HARD_FLOAT && TARGET_FPRS
&& registers_ok_for_quad_peep (operands[1], operands[3]) && registers_ok_for_quad_peep (operands[1], operands[3])
&& mems_ok_for_quad_peep (operands[0], operands[2])" && mems_ok_for_quad_peep (operands[0], operands[2])"
[(set (match_dup 0) [(set (match_dup 0)
@ -11935,7 +11899,7 @@
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y") [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
(match_operand:SF 2 "gpc_reg_operand" "f")))] (match_operand:SF 2 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fcmpu %0,%1,%2" "fcmpu %0,%1,%2"
[(set_attr "type" "fpcompare")]) [(set_attr "type" "fpcompare")])
@ -11943,7 +11907,7 @@
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y") [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
(match_operand:DF 2 "gpc_reg_operand" "f")))] (match_operand:DF 2 "gpc_reg_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "TARGET_HARD_FLOAT && TARGET_FPRS"
"fcmpu %0,%1,%2" "fcmpu %0,%1,%2"
[(set_attr "type" "fpcompare")]) [(set_attr "type" "fpcompare")])
@ -11953,7 +11917,7 @@
(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
(match_operand:TF 2 "gpc_reg_operand" "f")))] (match_operand:TF 2 "gpc_reg_operand" "f")))]
"!TARGET_IEEEQUAD && !TARGET_XL_COMPAT "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
"fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
[(set_attr "type" "fpcompare") [(set_attr "type" "fpcompare")
(set_attr "length" "12")]) (set_attr "length" "12")])
@ -11971,7 +11935,7 @@
(clobber (match_scratch:DF 9 "=f")) (clobber (match_scratch:DF 9 "=f"))
(clobber (match_scratch:DF 10 "=f"))] (clobber (match_scratch:DF 10 "=f"))]
"!TARGET_IEEEQUAD && TARGET_XL_COMPAT "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 3) (match_dup 13)) [(set (match_dup 3) (match_dup 13))

12
gcc/config/rs6000/rs6000.opt
View File

@ -260,15 +260,3 @@ Specify alignment of structure fields default/natural
mprioritize-restricted-insns= mprioritize-restricted-insns=
Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority)
Specify scheduling priority for dispatch slot restricted insns Specify scheduling priority for dispatch slot restricted insns
msingle-float
Target RejectNegative Var(rs6000_single_float)
Single-precision floating point unit
mdouble-float
Target RejectNegative Var(rs6000_double_float)
Double-precision floating point unit
msimple-fpu
Target RejectNegative Var(rs6000_simple_fpu)
Floating point unit does not support divide & sqrt

15
gcc/doc/invoke.texi
View File

@ -715,7 +715,6 @@ See RS/6000 and PowerPC Options.
-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol -m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
-malign-power -malign-natural @gol -malign-power -malign-natural @gol
-msoft-float -mhard-float -mmultiple -mno-multiple @gol -msoft-float -mhard-float -mmultiple -mno-multiple @gol
-msingle-float -mdouble-float -msimple-fpu @gol
-mstring -mno-string -mupdate -mno-update @gol -mstring -mno-string -mupdate -mno-update @gol
-mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol -mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol
-mstrict-align -mno-strict-align -mrelocatable @gol -mstrict-align -mno-strict-align -mrelocatable @gol
@ -13420,8 +13419,7 @@ following options:
@gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol @gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol
-mnew-mnemonics -mpopcntb -mpower -mpower2 -mpowerpc64 @gol -mnew-mnemonics -mpopcntb -mpower -mpower2 -mpowerpc64 @gol
-mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol -mpowerpc-gpopt -mpowerpc-gfxopt -mstring -mmulhw -mdlmzb -mmfpgpr}
-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr}
The particular options set for any particular CPU will vary between The particular options set for any particular CPU will vary between
compiler versions, depending on what setting seems to produce optimal compiler versions, depending on what setting seems to produce optimal
@ -13638,17 +13636,6 @@ Generate code that does not use (uses) the floating-point register set.
Software floating point emulation is provided if you use the Software floating point emulation is provided if you use the
@option{-msoft-float} option, and pass the option to GCC when linking. @option{-msoft-float} option, and pass the option to GCC when linking.
@item -msingle-float
@itemx -mdouble-float
@opindex msingle-float
@opindex mdouble-float
Generate code for single or double-precision floating point operations.
@option{-mdouble-float} implies @option{-msingle-float}.
@item -msimple-fpu
@opindex msimple-fpu
Do not generate sqrt and div instructions for hardware floating point unit.
@item -mmultiple @item -mmultiple
@itemx -mno-multiple @itemx -mno-multiple
@opindex mmultiple @opindex mmultiple