[AArch64] Rewrite vabs<q>_s<8,16,32,64> AdvSIMD intrinsics to fold to tree
gcc/ * config/aarch64/aarch64-builtins.c (aarch64_fold_builtin): Fold abs in all modes. * config/aarch64/aarch64-simd-builtins.def (abs): Enable for all modes. * config/aarch64/arm_neon.h (vabs<q>_s<8,16,32,64): Rewrite using builtins. (vabs_f64): Add missing intrinsic. gcc/testsuite/ * gcc.target/aarch64/vabs_intrinsic_1.c: New file. From-SVN: r201083
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
7a29a1b527
commit
d05d070973
@ -1,3 +1,13 @@
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2013-07-20 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-builtins.c
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(aarch64_fold_builtin): Fold abs in all modes.
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* config/aarch64/aarch64-simd-builtins.def
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(abs): Enable for all modes.
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* config/aarch64/arm_neon.h
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(vabs<q>_s<8,16,32,64): Rewrite using builtins.
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(vabs_f64): Add missing intrinsic.
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2013-07-19 Ian Bolton <ian.bolton@arm.com>
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* config/aarch64/arm_neon.h (vabs_s64): New function
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@ -1325,7 +1325,7 @@ aarch64_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args,
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switch (fcode)
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{
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BUILTIN_VDQF (UNOP, abs, 2)
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BUILTIN_VALLDI (UNOP, abs, 2)
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return fold_build1 (ABS_EXPR, type, args[0]);
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break;
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BUILTIN_VALLDI (BINOP, cmge, 0)
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@ -347,7 +347,7 @@
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BUILTIN_VDQF (UNOP, frecpe, 0)
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BUILTIN_VDQF (BINOP, frecps, 0)
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BUILTIN_VDQF (UNOP, abs, 2)
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BUILTIN_VALLDI (UNOP, abs, 2)
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VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
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VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
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@ -4468,83 +4468,6 @@ vabds_f32 (float32_t a, float32_t b)
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return result;
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}
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__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
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vabs_s8 (int8x8_t a)
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{
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int8x8_t result;
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__asm__ ("abs %0.8b,%1.8b"
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: "=w"(result)
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: "w"(a)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
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vabs_s16 (int16x4_t a)
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{
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int16x4_t result;
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__asm__ ("abs %0.4h,%1.4h"
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: "=w"(result)
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: "w"(a)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
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vabs_s32 (int32x2_t a)
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{
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int32x2_t result;
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__asm__ ("abs %0.2s,%1.2s"
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: "=w"(result)
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: "w"(a)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
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vabsq_s8 (int8x16_t a)
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{
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int8x16_t result;
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__asm__ ("abs %0.16b,%1.16b"
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: "=w"(result)
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: "w"(a)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
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vabsq_s16 (int16x8_t a)
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{
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int16x8_t result;
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__asm__ ("abs %0.8h,%1.8h"
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: "=w"(result)
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: "w"(a)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
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vabsq_s32 (int32x4_t a)
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{
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int32x4_t result;
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__asm__ ("abs %0.4s,%1.4s"
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: "=w"(result)
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: "w"(a)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
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vabsq_s64 (int64x2_t a)
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{
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int64x2_t result;
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__asm__ ("abs %0.2d,%1.2d"
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: "=w"(result)
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: "w"(a)
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: /* No clobbers */);
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return result;
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}
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__extension__ static __inline int16_t __attribute__ ((__always_inline__))
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vaddlv_s8 (int8x8_t a)
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{
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@ -17395,6 +17318,30 @@ vabs_f32 (float32x2_t __a)
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return __builtin_aarch64_absv2sf (__a);
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}
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__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
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vabs_f64 (float64x1_t __a)
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{
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return __builtin_fabs (__a);
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}
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__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
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vabs_s8 (int8x8_t __a)
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{
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return __builtin_aarch64_absv8qi (__a);
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}
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__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
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vabs_s16 (int16x4_t __a)
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{
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return __builtin_aarch64_absv4hi (__a);
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}
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__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
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vabs_s32 (int32x2_t __a)
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{
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return __builtin_aarch64_absv2si (__a);
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}
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__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
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vabs_s64 (int64x1_t __a)
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{
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@ -17413,6 +17360,30 @@ vabsq_f64 (float64x2_t __a)
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return __builtin_aarch64_absv2df (__a);
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}
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__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
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vabsq_s8 (int8x16_t __a)
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{
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return __builtin_aarch64_absv16qi (__a);
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}
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__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
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vabsq_s16 (int16x8_t __a)
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{
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return __builtin_aarch64_absv8hi (__a);
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}
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__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
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vabsq_s32 (int32x4_t __a)
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{
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return __builtin_aarch64_absv4si (__a);
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}
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__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
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vabsq_s64 (int64x2_t __a)
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{
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return __builtin_aarch64_absv2di (__a);
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}
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/* vadd */
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__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
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@ -1,3 +1,7 @@
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2013-07-20 James Greenhalgh <james.greenhalgh@arm.com>
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* gcc.target/aarch64/vabs_intrinsic_1.c: New file.
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2013-07-20 Joern Rennecke <joern.rennecke@embecosm.com>
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* gcc.dg/pr57154.c: Add dg-require-effective-target scheduling.
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101
gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_1.c
Normal file
101
gcc/testsuite/gcc.target/aarch64/vabs_intrinsic_1.c
Normal file
@ -0,0 +1,101 @@
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/* { dg-do run } */
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/* { dg-options "-O3 --save-temps" } */
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#include <arm_neon.h>
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extern void abort (void);
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#define ETYPE(size) int##size##_t
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#define VTYPE(size, lanes) int##size##x##lanes##_t
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#define TEST_VABS(q, size, lanes) \
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static void \
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test_vabs##q##_##size (ETYPE (size) * res, \
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const ETYPE (size) *in1) \
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{ \
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VTYPE (size, lanes) a = vld1##q##_s##size (res); \
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VTYPE (size, lanes) b = vld1##q##_s##size (in1); \
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a = vabs##q##_s##size (b); \
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vst1##q##_s##size (res, a); \
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}
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#define BUILD_VARS(width, n_lanes, n_half_lanes) \
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TEST_VABS (, width, n_half_lanes) \
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TEST_VABS (q, width, n_lanes) \
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BUILD_VARS (64, 2, 1)
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BUILD_VARS (32, 4, 2)
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BUILD_VARS (16, 8, 4)
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BUILD_VARS (8, 16, 8)
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#define POOL1 {-10}
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#define POOL2 {2, -10}
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#define POOL4 {0, -10, 2, -3}
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#define POOL8 {0, -10, 2, -3, 4, -50, 6, -70}
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#define POOL16 {0, -10, 2, -3, 4, -50, 6, -70, \
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-5, 10, -2, 3, -4, 50, -6, 70}
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#define EXPECTED1 {10}
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#define EXPECTED2 {2, 10}
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#define EXPECTED4 {0, 10, 2, 3}
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#define EXPECTED8 {0, 10, 2, 3, 4, 50, 6, 70}
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#define EXPECTED16 {0, 10, 2, 3, 4, 50, 6, 70, \
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5, 10, 2, 3, 4, 50, 6, 70}
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#define BUILD_TEST(size, lanes_64, lanes_128) \
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static void \
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test_##size (void) \
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{ \
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int i; \
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ETYPE (size) pool1[lanes_64] = POOL##lanes_64; \
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ETYPE (size) res1[lanes_64] = {0}; \
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ETYPE (size) expected1[lanes_64] = EXPECTED##lanes_64; \
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ETYPE (size) pool2[lanes_128] = POOL##lanes_128; \
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ETYPE (size) res2[lanes_128] = {0}; \
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ETYPE (size) expected2[lanes_128] = EXPECTED##lanes_128; \
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\
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/* Forcefully avoid optimization. */ \
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asm volatile ("" : : : "memory"); \
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test_vabs_##size (res1, pool1); \
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for (i = 0; i < lanes_64; i++) \
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if (res1[i] != expected1[i]) \
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abort (); \
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\
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/* Forcefully avoid optimization. */ \
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asm volatile ("" : : : "memory"); \
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test_vabsq_##size (res2, pool2); \
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for (i = 0; i < lanes_128; i++) \
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if (res2[i] != expected2[i]) \
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abort (); \
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}
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/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
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/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
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BUILD_TEST (8 , 8, 16)
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/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 1 } } */
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/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
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BUILD_TEST (16, 4, 8)
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/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 1 } } */
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/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
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BUILD_TEST (32, 2, 4)
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/* { dg-final { scan-assembler-times "abs\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" 1 } } */
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BUILD_TEST (64, 1, 2)
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#undef BUILD_TEST
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#define BUILD_TEST(size) test_##size ()
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int
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main (int argc, char **argv)
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{
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BUILD_TEST (8);
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BUILD_TEST (16);
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BUILD_TEST (32);
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BUILD_TEST (64);
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return 0;
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}
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/* { dg-final { cleanup-saved-temps } } */
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